522 lines
14 KiB
C++
522 lines
14 KiB
C++
/*
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* \brief Secured Digital Host Controller
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* \author Martin Stein
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* \date 2015-02-05
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*/
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/*
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* Copyright (C) 2015-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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/* local includes */
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#include <driver.h>
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using namespace Sd_card;
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using namespace Genode;
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int Driver::_wait_for_card_ready_mbw()
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{
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/*
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* Poll card status
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*
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* The maximum number of attempts and the delay between two attempts are
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* freely chosen.
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*/
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unsigned attempts = 5;
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uint64_t constexpr attempts_delay_us = 100000;
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while (1) {
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if (!attempts) {
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error("Reading card status after multiblock write failed");
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return -1;
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}
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/* assemble argument register value */
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Send_status::Arg::access_t cmdarg = 0;
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Send_status::Arg::Rca::set(cmdarg, _card_info.rca());
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/* assemble command register value */
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Xfertyp::access_t xfertyp = 0;
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Xfertyp::Cmdinx::set(xfertyp, Send_status::INDEX);
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Xfertyp::Cicen::set(xfertyp, 1);
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Xfertyp::Cccen::set(xfertyp, 1);
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Xfertyp::Rsptyp::set(xfertyp, Xfertyp::Rsptyp::_48BIT);
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Xfertyp::Msbsel::set(xfertyp, 1);
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Xfertyp::Bcen::set(xfertyp, 1);
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Xfertyp::Dmaen::set(xfertyp, 1);
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/* send command as soon as the host allows it */
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if (_wait_for_cmd_allowed()) { return -1; }
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Mmio::write<Cmdarg>(cmdarg);
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Mmio::write<Xfertyp>(xfertyp);
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/* wait for command completion */
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if (_wait_for_cmd_complete()) { return -1; }
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/* check for errors */
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R1_response_0::access_t const resp = Mmio::read<Cmdrsp0>();
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if (R1_response_0::Error::get(resp)) {
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error("Reading card status after multiblock write failed");
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return -1;
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}
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/* if card is in a ready state, return success, retry otherwise */
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if (R1_response_0::card_ready(resp)) { break; }
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_delayer.usleep(attempts_delay_us);
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}
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return 0;
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}
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int Driver::_stop_transmission()
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{
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/* write argument register */
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Mmio::write<Cmdarg>(0);
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/* write command register */
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Xfertyp::access_t xfertyp = 0;
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Xfertyp::Cmdinx::set(xfertyp, Stop_transmission::INDEX);
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Xfertyp::Cmdtyp::set(xfertyp, Xfertyp::Cmdtyp::ABORT_CMD12);
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Xfertyp::Cccen::set(xfertyp, 1);
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Xfertyp::Cicen::set(xfertyp, 1);
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Xfertyp::Rsptyp::set(xfertyp, Xfertyp::Rsptyp::_48BIT_BUSY);
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_stop_transmission_finish_xfertyp(xfertyp);
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Mmio::write<Xfertyp>(xfertyp);
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/* wait for command completion */
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if (_wait_for_cmd_complete()) { return -1; }
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return 0;
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}
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void Driver::_handle_irq()
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{
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_irq.ack_irq();
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/* the handler is only for block transfers, on other commands we poll */
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if (!_block_transfer.pending) {
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return; }
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/*
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* The host signals on multi-block transfers seem to be broken.
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* Synchronizing to "Transfer Complete" before returning from transfers
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* and to "Command Inhibit" before sending further commands - as it is
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* done with other controllers - isn't sufficient. Instead, both "Transfer
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* Complete" and "Command Complete" must be gathered.
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*/
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try {
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wait_for(Attempts(1000), Microseconds(1000), _delayer,
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Irqstat::Cc::Equal(1), Irqstat::Tc::Equal(1)); }
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catch (Polling_timeout) {
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error("Completion host signal timed out");
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throw -1;
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}
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/* acknowledge completion signals */
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Irqstat::access_t irqstat = 0;
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Irqstat::Cc::set(irqstat, 1);
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Irqstat::Tc::set(irqstat, 1);
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Mmio::write<Irqstat>(irqstat);
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if (_wait_for_cmd_complete_mb_finish(_block_transfer.read)) {
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throw -1; }
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_block_transfer.pending = false;
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ack_packet(_block_transfer.packet, true);
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}
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int Driver::_wait_for_cmd_complete()
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{
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try { wait_for(Attempts(200), Microseconds(5000), _delayer,
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Irqstat::Cc::Equal(1)); }
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catch (Polling_timeout) {
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error("command timed out");
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return -1;
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}
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Mmio::write<Irqstat>(Irqstat::Cc::reg_mask());
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return 0;
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}
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bool Driver::_issue_command(Command_base const & command)
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{
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/* get command characteristics */
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bool const transfer = command.transfer != TRANSFER_NONE;
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bool const reading = command.transfer == TRANSFER_READ;
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bool const multiblock =
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command.index == Read_multiple_block::INDEX ||
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command.index == Write_multiple_block::INDEX;
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/* set command index */
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Xfertyp::access_t xfertyp = 0;
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Xfertyp::Cmdinx::set(xfertyp, command.index);
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/* select response type */
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typedef Xfertyp::Rsptyp Rsptyp;
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Xfertyp::access_t rsptyp = 0;
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switch (command.rsp_type) {
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case RESPONSE_NONE: rsptyp = Rsptyp::_0BIT; break;
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case RESPONSE_136_BIT: rsptyp = Rsptyp::_136BIT; break;
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case RESPONSE_48_BIT: rsptyp = Rsptyp::_48BIT; break;
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case RESPONSE_48_BIT_WITH_BUSY: rsptyp = Rsptyp::_48BIT_BUSY; break;
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}
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Xfertyp::Rsptyp::set(xfertyp, rsptyp);
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/* generic transfer settings */
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if (command.transfer != TRANSFER_NONE) {
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Xfertyp::Dpsel::set(xfertyp);
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if (multiblock) {
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Xfertyp::Cicen::set(xfertyp, 1);
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Xfertyp::Cccen::set(xfertyp, 1);
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}
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}
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/* version-dependent transfer settings and issue command */
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_issue_cmd_finish_xfertyp(xfertyp, transfer, multiblock, reading);
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Mmio::write<Cmdarg>(command.arg);
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Mmio::write<Xfertyp>(xfertyp);
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/* for block transfers there's a signal handler, on other commands poll */
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return transfer ? true : !_wait_for_cmd_complete();
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}
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Cid Driver::_read_cid()
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{
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Cid cid;
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cid.raw_0 = Mmio::read<Rsp136_0>();
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cid.raw_1 = Mmio::read<Rsp136_1>();
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cid.raw_2 = Mmio::read<Rsp136_2>();
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cid.raw_3 = Mmio::read<Rsp136_3>();
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return cid;
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}
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Csd Driver::_read_csd()
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{
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Csd csd;
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csd.csd0 = Mmio::read<Rsp136_0>();
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csd.csd1 = Mmio::read<Rsp136_1>();
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csd.csd2 = Mmio::read<Rsp136_2>();
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csd.csd3 = Mmio::read<Rsp136_3>();
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return csd;
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}
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unsigned Driver::_read_rca()
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{
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Cmdrsp0::access_t const rsp0 = Mmio::read<Cmdrsp0>();
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return Send_relative_addr::Response::Rca::get(rsp0);
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}
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void Driver::read_dma(Block::sector_t blk_nr,
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size_t blk_cnt,
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addr_t buf_phys,
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Block::Packet_descriptor &packet)
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{
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if (_prepare_dma_mb(packet, true, blk_cnt, buf_phys)) {
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throw Io_error(); }
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if (!issue_command(Read_multiple_block(blk_nr))) {
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throw Io_error(); }
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}
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void Driver::write_dma(Block::sector_t blk_nr,
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size_t blk_cnt,
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addr_t buf_phys,
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Block::Packet_descriptor &packet)
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{
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if (_prepare_dma_mb(packet, false, blk_cnt, buf_phys)) {
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throw Io_error(); }
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if (!issue_command(Write_multiple_block(blk_nr))) {
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throw Io_error(); }
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}
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int Driver::_prepare_dma_mb(Block::Packet_descriptor packet,
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bool reading,
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size_t blk_cnt,
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addr_t buf_phys)
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{
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if (_block_transfer.pending) {
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throw Request_congestion(); }
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/* write ADMA2 table to DMA */
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size_t const req_size = blk_cnt * _block_size();
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if (_adma2_table.setup_request(req_size, buf_phys)) { return -1; }
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/* configure DMA at host */
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Mmio::write<Adsaddr>(_adma2_table.base_phys());
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Mmio::write<Blkattr::Blksize>(_block_size());
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Mmio::write<Blkattr::Blkcnt>(blk_cnt);
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_block_transfer.read = reading;
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_block_transfer.packet = packet;
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_block_transfer.pending = true;
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return 0;
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}
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int Driver::_wait_for_cmd_allowed()
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{
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/*
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* At least after multi-block writes on i.MX53 with the fix for the broken
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* "Auto Command 12", waiting only for "Command Inhibit" isn't sufficient
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* as "Data Line Active" and "Data Inhibit" may also be active.
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*/
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try { wait_for(_delayer, Prsstat::Dla::Equal(0),
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Prsstat::Sdstb::Equal(1),
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Prsstat::Cihb::Equal(0),
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Prsstat::Cdihb::Equal(0)); }
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catch (Polling_timeout) {
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error("wait till issuing a new command is allowed timed out");
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return -1;
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}
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return 0;
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}
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Card_info Driver::_init()
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{
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/* install IRQ signal */
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_irq.sigh(_irq_handler);
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_irq.ack_irq();
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/* configure host for initialization stage */
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if (_reset()) {
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_detect_err("Host reset failed"); }
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_disable_irqs();
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if (!_supported_host_version(Mmio::read<Hostver>())) {
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error("host version not supported");
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throw Detection_failed();
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}
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/*
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* We should check host capabilities at this point if we want to
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* support other versions of the SDHC. For the already supported
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* versions we know that the capabilities fit our requirements.
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*/
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/* configure IRQs, bus width, and clock for initialization */
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_enable_irqs();
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_bus_width(BUS_WIDTH_1);
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_delayer.usleep(10000);
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_clock(CLOCK_INITIAL);
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/*
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* Initialize card
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*/
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/*
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* At this point we should do an SDIO card reset if we later want
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* to detect the unwanted case of an SDIO card beeing inserted.
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* The reset would be done via 2 differently configured
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* Io_rw_direct commands.
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*/
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_delayer.usleep(1000);
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if (!issue_command(Go_idle_state())) {
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_detect_err("Go_idle_state command failed"); }
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_delayer.usleep(2000);
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if (!issue_command(Send_if_cond())) {
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_detect_err("Send_if_cond command failed"); }
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if (Mmio::read<Cmdrsp0>() != 0x1aa) {
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_detect_err("Unexpected response of Send_if_cond command"); }
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/*
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* At this point we could detect the unwanted case of an SDIO card
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* beeing inserted by issuing 4 Io_send_op_cond commands at an
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* interval of 10 ms (they should time out on SD).
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*/
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if (!issue_command(Sd_send_op_cond(0, false))) {
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_detect_err("Sd_send_op_cond command failed"); }
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_delayer.usleep(1000);
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if (!issue_command(Go_idle_state())) {
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_detect_err("Go_idle_state command failed"); }
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_delayer.usleep(2000);
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if (!issue_command(Send_if_cond())) {
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_detect_err("Send_if_cond failed"); }
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if (Mmio::read<Cmdrsp0>() != 0x1aa) {
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_detect_err("Unexpected response of Send_if_cond command"); }
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/*
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* Power on card
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*
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* We need to issue the same Sd_send_op_cond command multiple
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* times. The first time, we receive the status information. On
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* subsequent attempts, the response tells us that the card is
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* busy. Usually, the command is issued twice. We give up if the
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* card is not reaching busy state after one second.
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*/
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int i = 1000;
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for (; i > 0; --i) {
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if (!issue_command(Sd_send_op_cond(0x200000, true))) {
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_detect_err("Sd_send_op_cond command failed"); }
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if (Ocr::Busy::get(Mmio::read<Cmdrsp0>())) { break; }
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_delayer.usleep(1000);
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}
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if (!i) { _detect_err("Could not power-on SD card"); }
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/* get basic information about the card */
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Card_info card_info = _detect();
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/*
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* Configure working clock of host
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*
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* Host and card may be driven with a higher clock rate but
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* checks (maybe read SSR/SCR, read switch, try frequencies) are
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* necessary for that.
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*/
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_clock(CLOCK_OPERATIONAL);
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/*
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* Configure card and host to use 4 data signals
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*
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* Host and card may be driven with a higher bus width but
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* further checks (read SCR) are necessary for that.
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*/
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if (!issue_command(Set_bus_width(Set_bus_width::Arg::Bus_width::FOUR_BITS),
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card_info.rca()))
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{
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_detect_err("Set_bus_width(FOUR_BITS) command failed");
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}
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_bus_width(BUS_WIDTH_4);
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_delayer.usleep(10000);
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/* configure card to use given block size */
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if (!issue_command(Set_blocklen(_block_size()))) {
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_detect_err("Set_blocklen command failed"); }
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/* configure host buffer */
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Wml::access_t wml = Mmio::read<Wml>();
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_watermark_level(wml);
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Mmio::write<Wml>(wml);
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/* configure ADMA */
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Mmio::write<Proctl::Dmas>(Proctl::Dmas::ADMA2);
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/* configure interrupts for operational mode */
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_disable_irqs();
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Mmio::write<Irqstat>(~0);
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_enable_irqs();
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return card_info;
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}
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void Driver::_detect_err(char const * const err)
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{
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error(err);
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throw Detection_failed();
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}
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int Driver::_reset()
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{
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/* start reset */
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Mmio::write<Sysctl::Rsta>(1);
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_reset_amendments();
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/* wait for reset completion */
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try { wait_for(_delayer, Sysctl::Rsta::Equal(0)); }
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catch (Polling_timeout) {
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error("Reset timed out");
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return -1;
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}
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return 0;
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}
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void Driver::_disable_irqs()
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{
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Mmio::write<Irqstaten>(0);
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Mmio::write<Irqsigen>(0);
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}
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void Driver::_enable_irqs()
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{
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Irq::access_t irq = 0;
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Irq::Cc::set(irq, 1);
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Irq::Tc::set(irq, 1);
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Irq::Dint::set(irq, 1);
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Irq::Ctoe::set(irq, 1);
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Irq::Cce::set(irq, 1);
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Irq::Cebe::set(irq, 1);
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Irq::Cie::set(irq, 1);
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Irq::Dtoe::set(irq, 1);
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Irq::Dce::set(irq, 1);
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Irq::Debe::set(irq, 1);
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Irq::Ac12e::set(irq, 1);
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Irq::Dmae::set(irq, 1);
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Mmio::write<Irqstaten>(irq);
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Mmio::write<Irqsigen>(irq);
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}
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void Driver::_bus_width(Bus_width bus_width)
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{
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switch (bus_width) {
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case BUS_WIDTH_1: Mmio::write<Proctl::Dtw>(Proctl::Dtw::_1BIT); break;
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case BUS_WIDTH_4: Mmio::write<Proctl::Dtw>(Proctl::Dtw::_4BIT); break;
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}
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}
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void Driver::_disable_clock()
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{
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_disable_clock_preparation();
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Sysctl::access_t sysctl = Mmio::read<Sysctl>();
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Sysctl::Ipgen::set(sysctl, 0);
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Sysctl::Hcken::set(sysctl, 0);
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Sysctl::Peren::set(sysctl, 0);
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Sysctl::Dvs::set(sysctl, Sysctl::Dvs::DIV1);
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Sysctl::Sdclkfs::set(sysctl, Sysctl::Sdclkfs::DIV1);
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Mmio::write<Sysctl>(sysctl);
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}
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void Driver::_enable_clock(Clock_divider divider)
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{
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Sysctl::access_t sysctl = Mmio::read<Sysctl>();
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Sysctl::Ipgen::set(sysctl, 1);
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Sysctl::Hcken::set(sysctl, 1);
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Sysctl::Peren::set(sysctl, 1);
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switch (divider) {
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case CLOCK_DIV_4:
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Sysctl::Dvs::set(sysctl, Sysctl::Dvs::DIV4);
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Sysctl::Sdclkfs::set(sysctl, Sysctl::Sdclkfs::DIV1);
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break;
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case CLOCK_DIV_8:
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Sysctl::Dvs::set(sysctl, Sysctl::Dvs::DIV4);
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Sysctl::Sdclkfs::set(sysctl, Sysctl::Sdclkfs::DIV2);
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break;
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case CLOCK_DIV_512:
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Sysctl::Dvs::set(sysctl, Sysctl::Dvs::DIV16);
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Sysctl::Sdclkfs::set(sysctl, Sysctl::Sdclkfs::DIV32);
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break;
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}
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Mmio::write<Sysctl>(sysctl);
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_enable_clock_finish();
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_delayer.usleep(1000);
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}
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void Driver::_clock(Clock clock)
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{
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wait_for(_delayer, Prsstat::Sdstb::Equal(1));
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_disable_clock();
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_clock_finish(clock);
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}
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