75 lines
1.9 KiB
C++
75 lines
1.9 KiB
C++
/*
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* \brief Platform implementations specific for base-hw and Panda A2
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* \author Martin Stein
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* \date 2012-04-27
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*/
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/*
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* Copyright (C) 2012-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* core includes */
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#include <platform.h>
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#include <board.h>
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#include <cpu.h>
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#include <pic.h>
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#include <unmanaged_singleton.h>
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using namespace Genode;
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Native_region * Platform::_ram_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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{ Board::RAM_0_BASE, Board::RAM_0_SIZE }
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * mmio_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
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{ Board::MMIO_1_BASE, Board::MMIO_1_SIZE },
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{ Board::DSS_MMIO_BASE, Board::DSS_MMIO_SIZE },
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{ Board::DISPC_MMIO_BASE, Board::DISPC_MMIO_SIZE },
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{ Board::HDMI_MMIO_BASE, Board::HDMI_MMIO_SIZE }
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * Platform::_core_only_mmio_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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/* core timer and PIC */
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{ Board::CORTEX_A9_PRIVATE_MEM_BASE,
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Board::CORTEX_A9_PRIVATE_MEM_SIZE },
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/* core UART */
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{ Board::TL16C750_3_MMIO_BASE, Board::TL16C750_MMIO_SIZE },
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/* l2 cache controller */
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{ Board::PL310_MMIO_BASE, Board::PL310_MMIO_SIZE }
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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static Genode::L2_cache * l2_cache() {
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return unmanaged_singleton<Genode::L2_cache>(); }
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void Board::outer_cache_invalidate() { l2_cache()->invalidate(); }
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void Board::outer_cache_flush() { l2_cache()->flush(); }
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void Board::prepare_kernel() { l2_cache()->invalidate(); }
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Cpu::User_context::User_context() { cpsr = Psr::init_user(); }
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