1668983efa
This commit adds rocket core on the Zynq FPGA support to base HW. It also takes advantage of the new timer infrastructure introduced with the privileged 1.8 and adds improved TLB flush support. fixes #1880
24 lines
471 B
Makefile
24 lines
471 B
Makefile
#
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# \brief Build config for Genodes core process
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# \author Martin Stein
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# \author Sebastian Sumpf
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# \date 2011-12-16
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#
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# set target name that this configuration applies to
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TARGET = core
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# library that provides the whole configuration
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LIBS += core
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# add C++ sources
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SRC_CC += kernel/test.cc
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#
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# On RISCV we need a link address for core that differs from that of the other
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# components.
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#
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ifneq ($(filter riscv, $(SPECS)),)
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LD_TEXT_ADDR = $(CORE_LD_TEXT_ADDR)
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endif
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