151 lines
3.3 KiB
ArmAsm
151 lines
3.3 KiB
ArmAsm
/*
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* \brief Transition between kernel/userland, and secure/non-secure world
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* \author Martin Stein
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* \author Stefan Kalkowski
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* \date 2011-11-15
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*/
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/*
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* Copyright (C) 2011-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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.include "macros.s"
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/* size of pointer to CPU context */
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.set CONTEXT_PTR_SIZE, 1 * 8
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/* globally mapped buffer storage */
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.set BUFFER_SIZE, 6 * 8
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/* offsets of the member variables in a CPU context */
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.set SP_OFFSET, 1 * 8
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.set R8_OFFSET, 2 * 8
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.set RAX_OFFSET, 10 * 8
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.set ERRCODE_OFFSET, 17 * 8
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.set FLAGS_OFFSET, 18 * 8
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.set TRAPNO_OFFSET, 19 * 8
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.set CR3_OFFSET, 21 * 8
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.section .text
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/*
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* Page aligned base of mode transition code.
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*
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* This position independent code switches between a kernel context and a
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* user context and thereby between their address spaces. Due to the latter
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* it must be mapped executable to the same region in every address space.
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* To enable such switching, the kernel context must be stored within this
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* region, thus one should map it solely accessable for privileged modes.
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*/
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.p2align MIN_PAGE_SIZE_LOG2
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.global _mt_begin
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_mt_begin:
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/* space for a copy of the kernel context */
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.p2align 2
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.global _mt_master_context_begin
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_mt_master_context_begin:
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/* space must be at least as large as 'Cpu_state' */
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.space 22*8
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.global _mt_master_context_end
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_mt_master_context_end:
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/* space for a client context-pointer per CPU */
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.p2align 2
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.global _mt_client_context_ptr
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_mt_client_context_ptr:
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.space CONTEXT_PTR_SIZE
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/* a globally mapped buffer per CPU */
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.p2align 2
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.global _mt_buffer
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_mt_buffer:
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.space BUFFER_SIZE
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/*
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* On user exceptions the CPU has to jump to one of the following
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* seven entry vectors to switch to a kernel context.
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*/
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.global _mt_kernel_entry_pic
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_mt_kernel_entry_pic:
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/* Copy client context RAX to buffer */
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mov %rax, _mt_buffer
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/* Switch to kernel page tables */
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mov _mt_master_context_begin+CR3_OFFSET, %rax
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mov %rax, %cr3
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/* Save information on interrupt stack frame in client context */
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mov _mt_client_context_ptr, %rax
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popq TRAPNO_OFFSET(%rax)
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popq ERRCODE_OFFSET(%rax)
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popq (%rax)
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popq FLAGS_OFFSET(%rax) /* Discard cs */
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popq FLAGS_OFFSET(%rax)
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popq SP_OFFSET(%rax)
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1: jmp 1b
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.global _mt_user_entry_pic
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_mt_user_entry_pic:
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/* Prepare stack frame in mt buffer (Intel SDM Vol. 3A, figure 6-8) */
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mov _mt_client_context_ptr, %rax
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mov $_mt_buffer+BUFFER_SIZE, %rsp
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pushq $0x23
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pushq SP_OFFSET(%rax)
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/* Set I/O privilege level to 3 */
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orq $0x3000, FLAGS_OFFSET(%rax)
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btrq $9, FLAGS_OFFSET(%rax) /* XXX: Drop once interrupt handling is done */
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pushq FLAGS_OFFSET(%rax)
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pushq $0x1b
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pushq (%rax)
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/* Restore segment registers */
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mov $0x23, %rbx
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mov %rbx, %ds
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mov %rbx, %es
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mov %rbx, %fs
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mov %rbx, %gs
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/* Restore register values from client context */
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lea R8_OFFSET(%rax), %rsp
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popq %r8
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popq %r9
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popq %r10
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popq %r11
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popq %r12
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popq %r13
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popq %r14
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popq %r15
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popq _mt_buffer
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popq %rbx
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popq %rcx
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popq %rdx
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popq %rdi
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popq %rsi
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popq %rbp
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/* Switch page tables */
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mov CR3_OFFSET(%rax), %rax
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mov %rax, %cr3
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/* Set stack back to mt buffer and restore client RAX */
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mov $_mt_buffer, %rsp
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popq %rax
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iretq
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/* end of the mode transition code */
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.global _mt_end
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_mt_end:
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1: jmp 1b
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