0950b2f340
* Simplify IPU register definitions using templates * Distinguish between i.MX53 QSB and SMD board in driver * Support IPU specific overlay mechanism by framebuffer session extension
57 lines
1.5 KiB
C++
57 lines
1.5 KiB
C++
/*
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* \brief IOMUX controller register description
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* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
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* \date 2013-04-29
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _DRIVERS__PLATFORM__IMX53__IOMUX_H_
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#define _DRIVERS__PLATFORM__IMX53__IOMUX_H_
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/* Genode includes */
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#include <util/mmio.h>
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#include <drivers/board_base.h>
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#include <os/attached_io_mem_dataspace.h>
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class Iomux : public Genode::Attached_io_mem_dataspace,
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Genode::Mmio
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{
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private:
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struct Gpr2 : Register<0x8,32>
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{
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struct Ch1_mode : Bitfield<2, 2> {
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enum { ROUTED_TO_DI1 = 0x3 }; };
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struct Data_width_ch1 : Bitfield<7, 1> {
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enum { PX_18_BITS, PX_24_BITS }; };
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struct Bit_mapping_ch1 : Bitfield<8, 1> {
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enum { SPWG, JEIDA }; };
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struct Di1_vs_polarity : Bitfield<10,1> { };
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};
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public:
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Iomux()
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: Genode::Attached_io_mem_dataspace(Genode::Board_base::IOMUXC_BASE,
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Genode::Board_base::IOMUXC_SIZE),
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Genode::Mmio((Genode::addr_t)local_addr<void>())
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{
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}
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void enable_di1()
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{
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write<Gpr2::Di1_vs_polarity>(1);
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write<Gpr2::Data_width_ch1>(Gpr2::Data_width_ch1::PX_18_BITS);
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write<Gpr2::Bit_mapping_ch1>(Gpr2::Bit_mapping_ch1::SPWG);
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write<Gpr2::Ch1_mode>(Gpr2::Ch1_mode::ROUTED_TO_DI1);
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}
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};
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#endif /* _DRIVERS__PLATFORM__IMX53__IOMUX_H_ */
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