126 lines
3.6 KiB
C++
126 lines
3.6 KiB
C++
/*
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* \brief Kernel backend for execution contexts in userland
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* \author Martin Stein
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* \author Stefan Kalkowski
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* \date 2013-11-11
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <cpu/memory_barrier.h>
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#include <platform_pd.h>
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#include <kernel/cpu.h>
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#include <kernel/kernel.h>
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#include <kernel/pd.h>
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#include <kernel/thread.h>
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using namespace Kernel;
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extern "C" void kernel_to_user_context_switch(Cpu::Context*, Cpu::Fpu_context*);
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void Thread::exception(Cpu & cpu)
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{
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switch (regs->cpu_exception) {
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case Cpu::Context::SUPERVISOR_CALL:
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_call();
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return;
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case Cpu::Context::PREFETCH_ABORT:
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case Cpu::Context::DATA_ABORT:
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_mmu_exception();
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return;
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case Cpu::Context::INTERRUPT_REQUEST:
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case Cpu::Context::FAST_INTERRUPT_REQUEST:
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_interrupt(cpu.id());
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return;
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case Cpu::Context::UNDEFINED_INSTRUCTION:
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Genode::raw(*this, ": undefined instruction at ip=",
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Genode::Hex(regs->ip));
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_die();
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return;
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case Cpu::Context::RESET:
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return;
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default:
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Genode::raw(*this, ": triggered an unknown exception ",
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regs->cpu_exception);
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_die();
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return;
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}
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}
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void Kernel::Thread::_call_cache_coherent_region()
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{
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addr_t base = (addr_t) user_arg_1();
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size_t const size = (size_t) user_arg_2();
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/**
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* sanity check that only one small page is affected,
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* because we only want to lookup one page in the page tables
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* to limit execution time within the kernel
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*/
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if (Hw::trunc_page(base) != Hw::trunc_page(base+size-1)) {
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Genode::raw(*this, " tried to make cross-page region cache coherent ",
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(void*)base, " ", size);
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return;
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}
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/**
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* Lookup whether the page is backed, and if so make the memory coherent
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* in between I-, and D-cache
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*/
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addr_t phys = 0;
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if (pd().platform_pd().lookup_translation(base, phys)) {
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Cpu::cache_coherent_region(base, size);
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} else {
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Genode::raw(*this, " tried to make invalid address ",
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base, " cache coherent");
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}
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}
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/**
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* on ARM with multiprocessing extensions, maintainance operations on TLB,
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* and caches typically work coherently across CPUs when using the correct
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* coprocessor registers (there might be ARM SoCs where this is not valid,
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* with several shareability domains, but until now we do not support them)
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*/
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void Kernel::Thread::Tlb_invalidation::execute() { };
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void Thread::proceed(Cpu & cpu)
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{
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cpu.switch_to(*regs, pd().mmu_regs);
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regs->cpu_exception = cpu.stack_start();
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kernel_to_user_context_switch((static_cast<Cpu::Context*>(&*regs)),
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(static_cast<Cpu::Fpu_context*>(&*regs)));
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}
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void Thread::user_ret_time(Kernel::time_t const t)
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{
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regs->r0 = t >> 32UL;
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regs->r1 = t & ~0UL;
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}
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void Thread::user_arg_0(Kernel::Call_arg const arg) { regs->r0 = arg; }
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void Thread::user_arg_1(Kernel::Call_arg const arg) { regs->r1 = arg; }
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void Thread::user_arg_2(Kernel::Call_arg const arg) { regs->r2 = arg; }
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void Thread::user_arg_3(Kernel::Call_arg const arg) { regs->r3 = arg; }
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void Thread::user_arg_4(Kernel::Call_arg const arg) { regs->r4 = arg; }
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void Thread::user_arg_5(Kernel::Call_arg const arg) { regs->r5 = arg; }
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Kernel::Call_arg Thread::user_arg_0() const { return regs->r0; }
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Kernel::Call_arg Thread::user_arg_1() const { return regs->r1; }
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Kernel::Call_arg Thread::user_arg_2() const { return regs->r2; }
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Kernel::Call_arg Thread::user_arg_3() const { return regs->r3; }
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Kernel::Call_arg Thread::user_arg_4() const { return regs->r4; }
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Kernel::Call_arg Thread::user_arg_5() const { return regs->r5; }
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