164 lines
3.4 KiB
C++
164 lines
3.4 KiB
C++
/*
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* \brief CPU driver for core
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* \author Martin stein
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _CPU_H_
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#define _CPU_H_
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/* core includes */
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#include <spec/arm_v7/cpu_support.h>
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namespace Genode
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{
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/**
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* Part of CPU state that is not switched on every mode transition
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*/
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class Cpu_lazy_state { };
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/**
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* CPU driver for core
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*/
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class Cpu;
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}
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namespace Kernel { using Genode::Cpu_lazy_state; }
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class Genode::Cpu : public Arm_v7
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{
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public:
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/**
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* Translation table base control register
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*/
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struct Ttbcr : Arm::Ttbcr
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{
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struct Irgn0 : Bitfield<8, 2> { };
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struct Orgn0 : Bitfield<10, 2> { };
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struct Sh0 : Bitfield<12, 2> { };
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struct Eae : Bitfield<31, 1> { }; /* extended address enable */
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static access_t init_virt_kernel()
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{
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access_t v = 0;
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Irgn0::set(v, 1);
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Orgn0::set(v, 1);
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Sh0::set(v, 0b10);
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Eae::set(v, 1);
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return v;
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}
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};
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struct Mair0 : Register<32>
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{
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static void init()
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{
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access_t v = 0xff0044;
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asm volatile ("mcr p15, 0, %[v], c10, c2, 0" :: [v]"r"(v) : );
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}
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};
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/**
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* Non-secure access control register
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*/
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struct Nsacr : Arm_v7::Nsacr
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{
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struct Ns_smp : Bitfield<18,1> { };
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};
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/**
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* Translation table base register 0 (64-bit format)
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*/
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struct Ttbr0 : Register<64>
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{
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enum Memory_region { NON_CACHEABLE = 0, CACHEABLE = 1 };
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struct Ba : Bitfield<5, 34> { }; /* translation table base */
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struct Asid : Bitfield<48,8> { };
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static void write(access_t const v)
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{
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asm volatile ("mcrr p15, 0, %[v0], %[v1], c2"
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:: [v0]"r"(v), [v1]"r"(v >> 32) : );
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}
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static access_t read()
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{
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uint32_t v0, v1;
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asm volatile ("mrrc p15, 0, %[v0], %[v1], c2"
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: [v0]"=r"(v0), [v1]"=r"(v1) :: );
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return (access_t) v0 | ((access_t)v1 << 32);
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}
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/**
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* Return initialized value
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*
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* \param table base of targeted translation table
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*/
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static access_t init(addr_t const table, unsigned const id)
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{
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access_t v = Ba::masked((access_t)table);
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Asid::set(v, id);
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return v;
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}
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static Genode::uint32_t init(addr_t const table) {
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return table; }
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};
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/**
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* Return wether to retry an undefined user instruction after this call
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*/
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bool retry_undefined_instr(Cpu_lazy_state *) { return false; }
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/**
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* Return kernel name of the executing CPU
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*/
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static unsigned executing_id();
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/**
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* Return kernel name of the primary CPU
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*/
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static unsigned primary_id();
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/**
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* Switch to the virtual mode in kernel
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*
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* \param table base of targeted translation table
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* \param process_id process ID of the kernel address-space
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*/
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static void
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init_virt_kernel(addr_t const table, unsigned const process_id)
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{
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Mair0::init();
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Cidr::write(process_id);
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Dacr::write(Dacr::init_virt_kernel());
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Ttbr0::write(Ttbr0::init(table, 1));
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Ttbcr::write(Ttbcr::init_virt_kernel());
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Sctlr::write(Sctlr::init_virt_kernel());
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inval_branch_predicts();
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}
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/*************
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** Dummies **
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*************/
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static void tlb_insertions() { inval_branch_predicts(); }
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static void translation_added(addr_t, size_t) { }
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static void prepare_proceeding(Cpu_lazy_state *, Cpu_lazy_state *) { }
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};
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void Genode::Arm_v7::finish_init_phys_kernel() { }
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#endif /* _CPU_H_ */
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