Commit Graph

3341 Commits

Author SHA1 Message Date
Reto Buerki e5be376f57 hw_x86_64: Declare Thread_reg_id enum for x86_64
Only define IDs of registers which are actually accessed by threads.
2015-03-27 11:53:28 +01:00
Reto Buerki 472c3b6502 hw_x86_64: Use mtc relative addressing for master context 2015-03-27 11:53:28 +01:00
Reto Buerki 080d7d5f8b hw_x86_64: Use mtc relative addressing for _mt_buffer in crt0.s
Until the kernel page tables are active, labels can't be used directly
because the associated pages are not mapped for non-core threads.
2015-03-27 11:53:28 +01:00
Reto Buerki 09c90e5751 hw_x86_64: Set interrupt stack in Tss::Setup 2015-03-27 11:53:27 +01:00
Reto Buerki 9af9dcc02c hw_x86_64: Reserve space for interrupt stack in mtc region
The interrupt stack must reside in the mtc region in order to use it for
non-core threads. The size of the stack is set to 56 bytes in order to
hold the interrupt stack frame plus the additional vector number that is
pushed onto the stack by the ISR.
2015-03-27 11:53:27 +01:00
Reto Buerki 9c44d32dd9 hw_x86_64: Add virt_base paramater to Tss::setup function
The stack pointers (RSP) for privilege levels 0-2 must be setup using an
address in the mtc region to make stack switching work for non-core
threads.
2015-03-27 11:53:27 +01:00
Reto Buerki 15d131b723 hw_x86_64: Use _virt_mtc_addr to calculate ISR base
Call the _virt_mtc_addr function with the _mt_isrs label to calculate
the ISR base address in Idt::setup. Again, assume the address to be
below 0x10000.
2015-03-27 11:53:27 +01:00
Reto Buerki a5efe04656 hw_x86_64: Add virt_base paramater to Idt::setup function
Use parameter instead of class member variable because it would get
stored into the mtc region otherwise. In a further iteration only the
actual IDT should be saved into the mtc, not the complete class
instance. Currently the class instance size is equal to the IDT table
size.
2015-03-27 11:53:27 +01:00
Reto Buerki 1102b2b562 hw_x86_64: Calculate limit using _mt_gdt_end in Gdt::load 2015-03-27 11:53:27 +01:00
Reto Buerki 6f5ea78a51 hw_x86_64: Prefix gdt labels with _mt
Streamline the naming by prepending the _mt prefix to the gdt labels.
2015-03-27 11:53:26 +01:00
Reto Buerki 69e820e4e3 hw_x86_64: Reload GDTR in Genode::Cpu::init_thread
The GDT reload must happen after the page tables mapping the mtc region
is active, that's why it cannot be done in the Genode::Cpu ctor.
2015-03-27 11:53:26 +01:00
Reto Buerki 968ab15bbb hw_x86_64: Add Genode::Gdt class
The class provides the load() function which reloads the GDTR with the
GDT address in the mtc region. This is needed to make the segments
accessible to non-core threads.

Make the _gdt_start label global to use it in the call to
_virt_mtc_addr().
2015-03-27 11:53:26 +01:00
Reto Buerki 251b270e4b hw_x86_64: Factor out _virt_mtc_addr to mtc_util.h header 2015-03-27 11:53:26 +01:00
Reto Buerki cfe89996e8 hw_x86_64: Factor out pseudo descriptor class to own header 2015-03-27 11:53:26 +01:00
Reto Buerki d0f14cb941 hw_x86_64: Use _mt_tss and _mt_begin labels to set TSS base
The TSS descriptor base address is assumed to be below the 0x10000 mark
(only bits 0-15 used) for now.
2015-03-27 11:53:26 +01:00
Reto Buerki 00921e4a5c hw_x86_64: Create Tss instance in mtc region
Use the _mt_tss label and the placement new operator to create the
Tss class instance in the mtc region. Update the hard-coded
TSS base address to use the virtual mtc address.
2015-03-27 11:53:25 +01:00
Reto Buerki b9fe4a8d48 hw_x86_64: Reserve space for TSS in mtc region 2015-03-27 11:53:25 +01:00
Reto Buerki 34a25d3160 hw_x86_64: Make Tss member functions non-static
Add appropriate Tss object to Genode::Cpu class.
2015-03-27 11:53:25 +01:00
Reto Buerki ec028ea06f hw_x86_64: Move GDT into mtc region
The GDT must be visible for non-core threads too.
2015-03-27 11:53:25 +01:00
Reto Buerki bf5118fe54 hw_x86_64: Make _virt_idt_addr member more generic
Add label argument to function and rename it to _virt_mtc_addr. It can
be used to retrieve the virtual mtc address of any given label.
2015-03-27 11:53:25 +01:00
Reto Buerki b8e2249f51 hw_x86_64: Use _virt_idt_addr member in Idt::load
Load the virtual address in the mode transition pages into Interrupt
Descriptor Table Register (IDTR).
2015-03-27 11:53:25 +01:00
Reto Buerki 9c2d071654 hw_x86_64: Add virt_base argument to Idt::load
The argument specifies the virtual base address of the mode transition
pages.
2015-03-27 11:53:24 +01:00
Reto Buerki ecaad9ecce hw_x86_64: Add private _virt_idt_address member to Idt class
This function calculates the address of the IDT for a given virtual
mode transition base address.
2015-03-27 11:53:24 +01:00
Reto Buerki 89add00518 hw_x86_64: Create Idt instance in mtc region
Use the _mt_idt label and the placement new operator to create the Idt
instance in the mtc region.
2015-03-27 11:53:24 +01:00
Reto Buerki 9c8109c276 hw_x86_64: Reserve space for IDT on mode transition pages
On exception, the CPU first checks the IDT in order to find the
associated ISR. The IDT must therefore be placed in the mode transition
pages to make them available for non-core threads.
2015-03-27 11:53:24 +01:00
Reto Buerki d8a10448bb hw_x86_64: Make Idt member functions non-static
Add appropriate Idt object to Genode::Cpu class. Update the hard-coded
TSS base address.
2015-03-27 11:53:24 +01:00
Reto Buerki e3332c6c53 hw_x86_64: Drop obsolete isr.s assembly file 2015-03-27 11:53:24 +01:00
Reto Buerki a361fbd2bc hw_x86_64: Move ISR entries to mode transition page
This is needed to make them available for non-core threads which
initially only have the mode transition page mapped.
2015-03-27 11:53:23 +01:00
Reto Buerki d1a4eaed0d hw_x86_64: Add fake Timer::ms_to_tics implementation
This makes the scheduler happy and it starts scheduling threads.
2015-03-27 11:53:23 +01:00
Adrian-Ken Rueegsegger 4946f21302 hw_x86_64: Set base address and limit of TSS descriptor
The limit is set to match the TSS size - 1 and the base address is
hardcoded to the *current* address of the TSS instance (0x3a1100).

TODO: Set the base address using the 'tss' label. If the TSS descriptor
      format were not so utterly unusable this would be straightforward.
      Changes to the code that indirectly lead to a different location
      of the tss result in #GP since the base address will be invalid.
2015-03-27 11:53:23 +01:00
Adrian-Ken Rueegsegger 58e5f9b2fe hw_x86_64: Jump to actual kernel entry on interrupt 2015-03-27 11:53:23 +01:00
Adrian-Ken Rueegsegger 9f825ffb17 hw_x86_64: Setup and load Task State Segment 2015-03-27 11:53:23 +01:00
Adrian-Ken Rueegsegger 2af5aaa54d hw_x86_64: Add Tss class
The class Genode::Tss represents a 64-bit Task State Segment (TSS) as
specified by Intel SDM Vol. 3A, section 7.7.

The setup function sets the stack pointers for privilege levels 0-2 to
the kernel stack address. The load function loads the TSS segment
selector into the task register.
2015-03-27 11:53:23 +01:00
Adrian-Ken Rueegsegger 793b5264e3 hw_x86_64: Set dpl of syscall IDT entry to 3
Since this IDT entry is called from usermode the descriptor privilege
level must be 3.
2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger ed06c46233 hw_x86_64: Specify user argument to register mapping
Implement user argument setter and getter support functions. The mapping of
the state registers corresponds to the system call parameter passing
convention.
2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger 16a15237a4 hw_x86_64: Continue execution of the kernel
The instruction pointer is the first field of the master context and can
directly be used as a jump argument, which avoids additional register
copy operations.
2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger ecfb954eb9 hw_x86_64: Restore kernel stack pointer 2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger c62b4ea36a hw_x86_64: Restore kernel register values from master context
Set stack pointer to master context and restore kernel register by popping
the values from the master context.
2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger 7b051c0531 hw_x86_64: Restore kernel segment registers
The segment registers are set to reference the kernel data segments of
the GDT.
2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger fb5946b69c hw_x86_64: Save client register values to context
Point stack to client context region and save registers using push
instructions.

Note that since the push instruction first increments the stack pointer
and then stores the value on the stack, the RSP has to point one field
past RBP before pushing the first register value.
2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger 1035efcf3f hw_x86_64: Save info on interrupt stack to client context
As the kernel entry is called from the interrupt handler the stack
layout is as specified by Intel SDM Vol. 3A, figure 6-8. An additional
vector number is stored at the top of the stack.

Gather the necessary client information from the interrupt stack frame
and store it in the client context.
2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger 3d782282db hw_x86_64: Switch to kernel page tables
After switching to the kernel address space the client context region is
accessible to store the client register values.
2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger 16496af371 hw_x86_64: Create temporary copy of client RAX in kernel entry
Copy client context RAX value to buffer to enable use of RAX as scratch
register.
2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger 43bd925c7f hw_x86_64: Add offset constant for Cpu_state.trapno field 2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger 408cec32f5 base: Add errcode to x86_64 Cpu_state
The new errcode field is used to store the error code that some
interrupts provide (e.g. #PF). Rework mode transition reserved space and
offset constants to match the new CPU_state layout.
2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger 1d762ca254 hw_x86_64: Implement syscall with one to six arguments 2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger 04ad1340d5 hw_x86_64: Add syscall helper macros
The macros are used to assign syscall arguments to specific registers.
Using the AMD64 parameter passing convention avoids additional copying of
variables since the C++ function parameters are already in the right
registers.
2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger 3e779e3ca1 hw_x86_64: Perform the user entry mode transition
The interrupt return instruction in IA-32e mode applies the prepared
interrupt stack frame to set the RFLAGS, CS and SS segment as well as
the RIP and RSP registers. It then continues execution of the user code.

For detailed information refer to Intel SDM Vol. 3A, section 6.14.3.
2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger ab9d7afa45 hw_x86_64: Finally restore RAX client register value
Set the stack to the mode transition buffer and pop the temporary copy
of the RAX client value into the register.
2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger 1fc867f1d7 hw_x86_64: Switch to client page tables
After activating the client page tables the client context cannot be
accessed any longer. The mode transition buffer however is globally
mapped and can be used to restore the remaining register values.
2015-03-27 11:53:20 +01:00