Commit Graph

3375 Commits

Author SHA1 Message Date
Reto Buerki b9fe4a8d48 hw_x86_64: Reserve space for TSS in mtc region 2015-03-27 11:53:25 +01:00
Reto Buerki 34a25d3160 hw_x86_64: Make Tss member functions non-static
Add appropriate Tss object to Genode::Cpu class.
2015-03-27 11:53:25 +01:00
Reto Buerki ec028ea06f hw_x86_64: Move GDT into mtc region
The GDT must be visible for non-core threads too.
2015-03-27 11:53:25 +01:00
Reto Buerki bf5118fe54 hw_x86_64: Make _virt_idt_addr member more generic
Add label argument to function and rename it to _virt_mtc_addr. It can
be used to retrieve the virtual mtc address of any given label.
2015-03-27 11:53:25 +01:00
Reto Buerki b8e2249f51 hw_x86_64: Use _virt_idt_addr member in Idt::load
Load the virtual address in the mode transition pages into Interrupt
Descriptor Table Register (IDTR).
2015-03-27 11:53:25 +01:00
Reto Buerki 9c2d071654 hw_x86_64: Add virt_base argument to Idt::load
The argument specifies the virtual base address of the mode transition
pages.
2015-03-27 11:53:24 +01:00
Reto Buerki ecaad9ecce hw_x86_64: Add private _virt_idt_address member to Idt class
This function calculates the address of the IDT for a given virtual
mode transition base address.
2015-03-27 11:53:24 +01:00
Reto Buerki 89add00518 hw_x86_64: Create Idt instance in mtc region
Use the _mt_idt label and the placement new operator to create the Idt
instance in the mtc region.
2015-03-27 11:53:24 +01:00
Reto Buerki 9c8109c276 hw_x86_64: Reserve space for IDT on mode transition pages
On exception, the CPU first checks the IDT in order to find the
associated ISR. The IDT must therefore be placed in the mode transition
pages to make them available for non-core threads.
2015-03-27 11:53:24 +01:00
Reto Buerki d8a10448bb hw_x86_64: Make Idt member functions non-static
Add appropriate Idt object to Genode::Cpu class. Update the hard-coded
TSS base address.
2015-03-27 11:53:24 +01:00
Reto Buerki e3332c6c53 hw_x86_64: Drop obsolete isr.s assembly file 2015-03-27 11:53:24 +01:00
Reto Buerki a361fbd2bc hw_x86_64: Move ISR entries to mode transition page
This is needed to make them available for non-core threads which
initially only have the mode transition page mapped.
2015-03-27 11:53:23 +01:00
Reto Buerki d1a4eaed0d hw_x86_64: Add fake Timer::ms_to_tics implementation
This makes the scheduler happy and it starts scheduling threads.
2015-03-27 11:53:23 +01:00
Adrian-Ken Rueegsegger 4946f21302 hw_x86_64: Set base address and limit of TSS descriptor
The limit is set to match the TSS size - 1 and the base address is
hardcoded to the *current* address of the TSS instance (0x3a1100).

TODO: Set the base address using the 'tss' label. If the TSS descriptor
      format were not so utterly unusable this would be straightforward.
      Changes to the code that indirectly lead to a different location
      of the tss result in #GP since the base address will be invalid.
2015-03-27 11:53:23 +01:00
Adrian-Ken Rueegsegger 58e5f9b2fe hw_x86_64: Jump to actual kernel entry on interrupt 2015-03-27 11:53:23 +01:00
Adrian-Ken Rueegsegger 9f825ffb17 hw_x86_64: Setup and load Task State Segment 2015-03-27 11:53:23 +01:00
Adrian-Ken Rueegsegger 2af5aaa54d hw_x86_64: Add Tss class
The class Genode::Tss represents a 64-bit Task State Segment (TSS) as
specified by Intel SDM Vol. 3A, section 7.7.

The setup function sets the stack pointers for privilege levels 0-2 to
the kernel stack address. The load function loads the TSS segment
selector into the task register.
2015-03-27 11:53:23 +01:00
Adrian-Ken Rueegsegger 793b5264e3 hw_x86_64: Set dpl of syscall IDT entry to 3
Since this IDT entry is called from usermode the descriptor privilege
level must be 3.
2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger ed06c46233 hw_x86_64: Specify user argument to register mapping
Implement user argument setter and getter support functions. The mapping of
the state registers corresponds to the system call parameter passing
convention.
2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger 16a15237a4 hw_x86_64: Continue execution of the kernel
The instruction pointer is the first field of the master context and can
directly be used as a jump argument, which avoids additional register
copy operations.
2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger ecfb954eb9 hw_x86_64: Restore kernel stack pointer 2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger c62b4ea36a hw_x86_64: Restore kernel register values from master context
Set stack pointer to master context and restore kernel register by popping
the values from the master context.
2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger 7b051c0531 hw_x86_64: Restore kernel segment registers
The segment registers are set to reference the kernel data segments of
the GDT.
2015-03-27 11:53:22 +01:00
Adrian-Ken Rueegsegger fb5946b69c hw_x86_64: Save client register values to context
Point stack to client context region and save registers using push
instructions.

Note that since the push instruction first increments the stack pointer
and then stores the value on the stack, the RSP has to point one field
past RBP before pushing the first register value.
2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger 1035efcf3f hw_x86_64: Save info on interrupt stack to client context
As the kernel entry is called from the interrupt handler the stack
layout is as specified by Intel SDM Vol. 3A, figure 6-8. An additional
vector number is stored at the top of the stack.

Gather the necessary client information from the interrupt stack frame
and store it in the client context.
2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger 3d782282db hw_x86_64: Switch to kernel page tables
After switching to the kernel address space the client context region is
accessible to store the client register values.
2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger 16496af371 hw_x86_64: Create temporary copy of client RAX in kernel entry
Copy client context RAX value to buffer to enable use of RAX as scratch
register.
2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger 43bd925c7f hw_x86_64: Add offset constant for Cpu_state.trapno field 2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger 408cec32f5 base: Add errcode to x86_64 Cpu_state
The new errcode field is used to store the error code that some
interrupts provide (e.g. #PF). Rework mode transition reserved space and
offset constants to match the new CPU_state layout.
2015-03-27 11:53:21 +01:00
Adrian-Ken Rueegsegger 1d762ca254 hw_x86_64: Implement syscall with one to six arguments 2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger 04ad1340d5 hw_x86_64: Add syscall helper macros
The macros are used to assign syscall arguments to specific registers.
Using the AMD64 parameter passing convention avoids additional copying of
variables since the C++ function parameters are already in the right
registers.
2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger 3e779e3ca1 hw_x86_64: Perform the user entry mode transition
The interrupt return instruction in IA-32e mode applies the prepared
interrupt stack frame to set the RFLAGS, CS and SS segment as well as
the RIP and RSP registers. It then continues execution of the user code.

For detailed information refer to Intel SDM Vol. 3A, section 6.14.3.
2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger ab9d7afa45 hw_x86_64: Finally restore RAX client register value
Set the stack to the mode transition buffer and pop the temporary copy
of the RAX client value into the register.
2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger 1fc867f1d7 hw_x86_64: Switch to client page tables
After activating the client page tables the client context cannot be
accessed any longer. The mode transition buffer however is globally
mapped and can be used to restore the remaining register values.
2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger 172dec209b hw_x86_64: Restore registers to client context values
Set the stack pointer to the R8 field in the client context to enable
restoring registers by popping values of the stack.

After this step the only remaining registers that do not contain client
values are RAX, RSP and RIP.

Note that the client value of RAX is pop'd to the global buffer region as
the register will still be used by subsequent steps. It will be restored to
the value in the buffer area just prior to resuming client code execution.
2015-03-27 11:53:20 +01:00
Adrian-Ken Rueegsegger 60e799f7b4 hw_x86_64: Set segment registers prior to mode transition
The registers for the ds, es, fs and gs segments are hardcoded to GDT
index 4 with requested privilege level set to 3.
2015-03-27 11:53:19 +01:00
Adrian-Ken Rueegsegger fe22858550 hw_x86_64: Adjust EFLAGS of prepared interrupt stack frame
Set I/O privilege level to 3 to allow core to perform port I/O from
userspace. Also make sure the IF flag is cleared for now until interrupt
handling is implemented.
2015-03-27 11:53:19 +01:00
Adrian-Ken Rueegsegger 40862a81eb hw_x86_64: Prepare interrupt stack frame in mode transition buffer
Setup an IA-32e interrupt stack frame in the mode transition buffer region.
It will be used to perform the mode switch to userspace using the iret
instruction.

For detailed information about the IA-32e interrupt stack frame refer to
Intel SDM Vol. 3A, figure 6-8.
2015-03-27 11:53:19 +01:00
Adrian-Ken Rueegsegger 4b7a5ced3b hw_x86_64: Declare CPU context offset constants
The constants specify offset values of CPU context member variables as
specified by Genode::Cpu_state [1] and Genode::Cpu::Context [2].

[1] - repos/base/include/x86_64/cpu/cpu_state.h
[2] - repos/base-hw/src/core/include/spec/x86/cpu.h
2015-03-27 11:53:19 +01:00
Adrian-Ken Rueegsegger e3f10b5ce2 hw_x86_64: Reserve space for mode transition buffer
Since the buffer stores an IA-32e interrupt stack frame, its size must
be 6 * 8 bytes.
2015-03-27 11:53:19 +01:00
Adrian-Ken Rueegsegger 03929b3cc9 hw_x86_64: Add 64-bit user code and data segments to GDT
The new entries specify a 64-bit code segment with DPL 3 at index 3 and a
64-bit data segment with DPL 3 at index 4.

These segments are needed for transitioning to user mode.
2015-03-27 11:53:19 +01:00
Adrian-Ken Rueegsegger 51d515c77f hw_x86_64: Explicitly set up segment selectors during boot 2015-03-27 11:53:18 +01:00
Adrian-Ken Rueegsegger 65de09c7a6 hw_x86_64: Reserve space for client context pointer
A pointer to the client context is placed in the mt_client_context_ptr area.
It is used to pass the current client context to the lowlevel mode-switching
assembly code.
2015-03-27 11:53:18 +01:00
Adrian-Ken Rueegsegger 4417fe6201 hw_x86_64: Implementation of IA-32e paging
IA-32e paging translates 48-bit linear addresses to 52-bit physical
addresses. Translation structures are hierarchical and four levels deep.
The current implementation supports regular 4KB and 1 GB and 2 MB large
page mappings.

Memory typing is not yet implemented since the encoded type bits depend
on the active page attribute table (PAT)*.

For detailed information refer to Intel SDM Vol. 3A, section 4.5.

* The default PAT after power up does not allow the encoding of the
  write-combining memory type, see Intel SDM Vol. 3A, section 11.12.4.
* Add common IA-32e paging descriptor type:
    The type represents a table entry and encompasses all fields shared by
    paging structure entries of all four levels (PML4, PDPT, PD and PT).
* Simplify PT entry type by using common descriptor:
    Differing fields are the physical address, the global flag and the memory
    type flags.
* Simplify directory entry type by using common descriptor:
    Page directory entries (PDPT and PD) have an additional 'page size' field
    that specifies if the entry references a next level paging structure or
    represents a large page mapping.
* Simplify PML4 entry type by using common descriptor
    Top-level paging structure entries (PML4) do not have a 'pat' flag and the
    memory type is specified by the 'pwt' and 'pcd' fields only.
* Implement access right merging for directory paging entries
    The access rights for translations are determined by the U/S, R/W and XD
    flags. Paging structure entries that reference other tables must provide
    the superset of rights required for all entries of the referenced table.
    Thus merge access rights of new mappings into existing directory entries to
    grant additional rights if needed.
* Add cr3 register definition:
    The control register 3 is used to set the current page-directory base
    register.
* Add cr3 variable to x86_64 Cpu Context
    The variable designates the address of the top-level paging structure.
* Return current cr3 value as translation table base
* Set context cr3 value on translation table assignment
* Implement switch to virtual mode in kernel
    Activate translation table in init_virt_kernel function by updating the
    cr3 register.
* Ignore accessed and dirty flags when comparing existing table entries
    These flags can be set by the MMU and must be disregarded.
2015-03-27 11:53:18 +01:00
Reto Buerki c7cadf52a6 hw_x86_64: setup ISR and IDT
* Add isr.s assembler file:
    The file declares an array of Interrupt Service Routines (ISR) to handle
    the exception vectors from 0 to 19, see Intel SDM Vol. 3A, section
    6.3.1.
* Add Idt class:
  * The class Genode::Idt represents an Interrupt Descriptor Table as
    specified by Intel SDM Vol. 3A, section 6.10.
  * The setup function initializes the IDT with 20 entries using the ISR
    array defined in the isr.s assembly file.
* Setup and load IDT in Genode::Cpu ctor:
    The Idt::setup function is only executed once on the BSP.
* Declare ISRs for interrupts 20-255
* Set IDT size to 256
2015-03-27 11:53:18 +01:00
Reto Buerki 6e0f1a4466 hw_x86_64: Adjust size of _mt_master_context
The CPU state in IA-32e mode consists of 20 64-bit registers.
2015-03-27 11:53:18 +01:00
Reto Buerki 0f624cdde7 hw_x86_64: Perform indirect long jump to 64-bit code 2015-03-27 11:53:18 +01:00
Reto Buerki 15d0e86592 hw_x86_64: Load Global Descriptor Table register 2015-03-27 11:53:17 +01:00
Reto Buerki 27191b17ce hw_x86_64: Declare Global Descriptor Table (GDT) in .data
The table specifies a 64-bit code segment descriptor at index 1, a
64-bit data segment descriptor at index 2 and a task segment descriptor
at index 3.
2015-03-27 11:53:17 +01:00
Reto Buerki 59bba7624f hw_x86_64: Set system control flags of cr0 register
Enable paging, write protection, caching and native FPU error reporting,
see Intel SDM Vol. 3A, section 2.5.
2015-03-27 11:53:17 +01:00