Commit Graph

4 Commits

Author SHA1 Message Date
Mark Vels 1668983efa base-hw: RISC-V Rocket Core on Zynq
This commit adds rocket core on the Zynq FPGA support to base HW. It also takes
advantage of the new timer infrastructure introduced with the privileged 1.8 and
adds improved TLB flush support.

fixes #1880
2016-02-26 11:36:51 +01:00
Sebastian Sumpf c246a0d194 base-hw: initial RISC-V support
using the spike instruction emulator

issue #1880
2016-02-26 11:36:51 +01:00
Martin Stein 0ab5310b8a hw: enable kernel-internal tests via run tool
Kernel tests are done by replacing the implementation of an otherwise
empty function 'Kernel::test' that gets called once at the primary CPU
as soon as all kernel initialization is done. To achieve this, the test
binary that implements 'Kernel::test' must be linked against the core
lib and must then replace the core binary when composing the boot image.
The latter can be done conveniently in a run script by setting the new
argument 'core_type' of the function 'build_boot_image' to the falue
'test'. If no kernel test is needed the argument does not have to be
given - it is set to 'core' by default which results in a "normal"
Genode image.

ref #1225
2014-11-28 12:02:34 +01:00
Martin Stein 6cb9559feb hw: core as library
The build config for core is now provided through libraries to enable
implicit config composition through specifiers and thereby avoid
consideration of inappropriate targets.

fix #1199
2014-07-24 10:18:06 +02:00