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Commit Graph

Author	SHA1	Message	Date
Mark Vels	1668983efa	base-hw: RISC-V Rocket Core on Zynq This commit adds rocket core on the Zynq FPGA support to base HW. It also takes advantage of the new timer infrastructure introduced with the privileged 1.8 and adds improved TLB flush support. fixes #1880	2016-02-26 11:36:51 +01:00
Sebastian Sumpf	c246a0d194	base-hw: initial RISC-V support using the spike instruction emulator issue #1880	2016-02-26 11:36:51 +01:00

Author

SHA1

Message

Date

Mark Vels

1668983efa

base-hw: RISC-V Rocket Core on Zynq

This commit adds rocket core on the Zynq FPGA support to base HW. It also takes
advantage of the new timer infrastructure introduced with the privileged 1.8 and
adds improved TLB flush support.

fixes #1880

2016-02-26 11:36:51 +01:00

Sebastian Sumpf

c246a0d194

base-hw: initial RISC-V support

using the spike instruction emulator

issue #1880

2016-02-26 11:36:51 +01:00

2 Commits