Commit Graph

17 Commits

Author SHA1 Message Date
Martin Stein
d30edd4841 hw: make RM faults less noisy in release mode
If an RM fault ends up in any trouble, the faulter remains paused and
the pager activation continues with the next fault. Thus we can print
a warning instead of an error and safe execution time in release mode.

ref #1096
2014-04-07 17:02:00 +02:00
Martin Stein
6e21ab42d2 hw: apply MMU cache-flushes to all processors
ref #1076
2014-03-14 13:16:05 +01:00
Stefan Kalkowski
2ed22595ff hw: simplify Page_flags (fix #711)
Instead of using a special bitfield use a compound of boolean
values for the generic page attributes. To reduce copy overhead,
change the corresponding functions, where Page_flags are used as
arguments, to use references.
2014-03-03 14:11:22 +01:00
Martin Stein
87da21d967 hw: use platform-thread pointer as pager badge
ref #953
2013-11-25 09:45:30 +01:00
Martin Stein
909ab8dcd0 hw: communicate page faults via signals
Enable routing of thread events to signal contexts via
Kernel::route_thread_event.

Replace Kernel::set_pager by Kernel::route_thread_event.

In base-hw a pager object is a signal context and a pager activation
is a signal receiver. If a thread wants to start communicating its page
faults via a pager object, the thread calls Kernel::route_thread_event with
its thread ID, event ID "FAULT", and the signal context ID of the pager object.
If a pager activation wants to start handling page faults of a pager object,
the pager activation assigns the corresponding signal context to its signal
receiver. If a pager activation wants to stop handling page faults of a pager
object, the pager activation dissolves the corresponding signal context from
its signal receiver. If a thread wants to start communicating its page faults
via a pager object, the thread calls Kernel::route_thread_event with its
thread ID, event ID "FAULT", and the invalid signal context ID.

Remove Kernel::resume_faulter.

Move all page fault related code from generic kernel sources to CPU
specific cpu_support.h and cpu_support.cc.

fix #935
2013-11-14 19:57:31 +01:00
Martin Stein
002a5b8978 hw: distinct pagefault and IPC message type
ref #874
2013-11-14 19:56:39 +01:00
Martin Stein
d86bf3db64 hw: destruct protection domains
ref #589
2013-09-26 16:09:55 +02:00
Martin Stein
f7fd7b0b11 hw: no assertions in pagers
ref #528
2013-09-26 15:58:03 +02:00
Martin Stein
545a397fa6 hw: avoid mandatory function calls in assertions
ref #528
2013-09-26 15:58:03 +02:00
Norman Feske
73ab30c22c Update copyright headers to 2013 2013-01-10 21:44:47 +01:00
Martin Stein
7f2f2d9120 base-hw: ease core build
Merge core only libs into the target make-files.

Use base-hw specific Board drivers that inherit
from generic Board_base.

Use Page_flags::access_t instead of additional
page_flags_t.

Fix #570
2013-01-08 11:36:52 +01:00
Norman Feske
0dbb5e1696 Propagate 'Range_allocator::alloc_aligned' errors
This patch reflects eventual allocation errors in a more specific way to
the caller of 'alloc_aligned', in particular out-of-metadata and
out-of-memory are considered as different conditions.

Related to issue #526.
2012-11-28 22:51:09 +01:00
Martin Stein
6cb89f79e3 base_hw & arm_v7: Use write-back caching.
Add 'resume_faulter' syscall that is similar to 'resume_thread', but
is called only when resuming a thread after resolving its pagefault.
This way the kernel can flush caches after resolving a pagefault. This is
because by now the MMU doesn't use caches when doing a pagetable walk.
2012-11-22 09:21:53 +01:00
Martin Stein
4723b08322 base_hw: Use TLB-specific 'struct Page_flags'.
'Page_flags' maps application-specific memory attributes
to the TLB-specific memory attributes. Thereby it avoids
functions with lots of parameters, by declaring appropriate
bitfields on a single POD value.
2012-11-22 09:21:53 +01:00
Martin Stein
4d2a3de0ee base_hw: Rename 'Software_tlb' 'Tlb'. 2012-11-14 16:36:51 +01:00
Martin Stein
53156de9f4 base_hw & arm: Memory attributes and light caching.
Enable caches. Core is not cached by now. This is because kernel
creates core space and doesn't know any memory attributes by now.
Cacheable pages are cached write-through without write-allocate.

Caching and write-combining is not supported for IOMEM by now.
2012-11-14 16:36:51 +01:00
Martin Stein
ff65f6f021 Run Genode directly on hardware with 'base-hw'. 2012-08-03 12:06:37 +02:00