From fabea7fba1993a0c31d71a628019393f29d0ee39 Mon Sep 17 00:00:00 2001 From: Martin Stein Date: Fri, 4 Apr 2014 17:33:59 +0200 Subject: [PATCH] hw: provide invalidate_instr_caches_by_virt_region ref #1115 --- base-hw/src/core/processor_driver/arm.h | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/base-hw/src/core/processor_driver/arm.h b/base-hw/src/core/processor_driver/arm.h index 6ea596148..e27664222 100644 --- a/base-hw/src/core/processor_driver/arm.h +++ b/base-hw/src/core/processor_driver/arm.h @@ -280,6 +280,21 @@ namespace Arm } }; + /** + * Instruction Cache Invalidate by MVA to PoU + */ + struct Icimvau : Register<32> + { + /** + * Write register value + */ + static void write(access_t const v) + { + asm volatile ( + "mcr p15, 0, %[v], c7, c5, 1\n" :: [v] "r" (v) : ); + } + }; + /** * Data Cache Clean by MVA to PoC */ @@ -668,6 +683,21 @@ namespace Arm base = base & LINE_ALIGNM_MASK; for (; base < top; base += LINE_SIZE) { Dccmvac::write(base); } } + + /** + * Invalidate every instruction-cache entry within a virtual region + */ + static void + invalidate_instr_caches_by_virt_region(addr_t base, size_t const size) + { + enum { + LINE_SIZE = 1 << Board::CACHE_LINE_SIZE_LOG2, + LINE_ALIGNM_MASK = ~(LINE_SIZE - 1), + }; + addr_t const top = base + size; + base = base & LINE_ALIGNM_MASK; + for (; base < top; base += LINE_SIZE) { Icimvau::write(base); } + } }; }