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hw: remove overall cache maintainance from core 

This functionality is only needed in bootstrap now that kernel and
userland share the same address-space.

Fix #2699
This commit is contained in:
Stefan Kalkowski 2019-03-13 15:43:56 +01:00 committed by Norman Feske
parent 9bbc91bb52
commit e9b3569f44
28 changed files with 27 additions and 289 deletions
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1
repos/base-hw/lib/mk/spec/arm_v6/core-hw.inc
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@ -9,7 +9,6 @@
INC_DIR += $(BASE_DIR)/../base-hw/src/core/spec/arm_v6
# add C++ sources
SRC_CC += spec/arm_v6/cpu.cc
SRC_CC += spec/arm_v6/perf_counter.cc
SRC_CC += kernel/vm_thread_off.cc
SRC_CC += kernel/cpu_up.cc

1
repos/base-hw/lib/mk/spec/arm_v7/core-hw.inc
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@ -8,7 +8,6 @@
INC_DIR += $(BASE_DIR)/../base-hw/src/core/spec/arm_v7
# add C++ sources
SRC_CC += spec/arm_v7/cpu.cc
SRC_CC += spec/arm_v7/perf_counter.cc
SRC_S += spec/arm/vfpv3-d32.cc

2
repos/base-hw/lib/mk/spec/arndale/bootstrap-hw.mk
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@ -3,7 +3,7 @@ INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/arndale
SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc
SRC_CC += bootstrap/spec/arndale/pic.cc
SRC_CC += bootstrap/spec/arndale/platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
SRC_S += bootstrap/spec/arm/crt0.s

2
repos/base-hw/lib/mk/spec/imx53_qsb/bootstrap-hw.mk
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@ -5,7 +5,7 @@ SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cortex_a8_mmu.cc
SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/imx_tzic.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
ifneq ($(filter-out $(SPECS),trustzone),)

2
repos/base-hw/lib/mk/spec/imx6q_sabrelite/bootstrap-hw.mk
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@ -6,7 +6,7 @@ SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/arm/imx6_platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
NR_OF_CPUS = 4

2
repos/base-hw/lib/mk/spec/nit6_solox/bootstrap-hw.mk
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@ -6,7 +6,7 @@ SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/arm/imx6_platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
NR_OF_CPUS = 1

2
repos/base-hw/lib/mk/spec/odroid_xu/bootstrap-hw.mk
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@ -3,7 +3,7 @@ INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/odroid_xu
SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/odroid_xu/platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
SRC_S += bootstrap/spec/arm/crt0.s

2
repos/base-hw/lib/mk/spec/panda/bootstrap-hw.mk
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@ -5,7 +5,7 @@ SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/panda/platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
SRC_S += bootstrap/spec/arm/crt0.s

2
repos/base-hw/lib/mk/spec/pbxa9/bootstrap-hw.mk
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@ -6,7 +6,7 @@ SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/pbxa9/platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc

2
repos/base-hw/lib/mk/spec/rpi/bootstrap-hw.mk
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@ -1,7 +1,7 @@
INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/rpi
SRC_CC += bootstrap/spec/rpi/platform.cc
SRC_CC += hw/spec/arm/arm_v6_cpu.cc
SRC_CC += bootstrap/spec/arm/arm_v6_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
SRC_S += bootstrap/spec/arm/crt0.s

2
repos/base-hw/lib/mk/spec/usb_armory/bootstrap-hw.mk
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@ -6,7 +6,7 @@ SRC_CC += bootstrap/spec/arm/cortex_a8_mmu.cc
SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/imx_tzic.cc
SRC_CC += bootstrap/spec/usb_armory/platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc

2
repos/base-hw/lib/mk/spec/wand_quad/bootstrap-hw.mk
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@ -6,7 +6,7 @@ SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/arm/imx6_platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
NR_OF_CPUS = 4

2
repos/base-hw/lib/mk/spec/zynq_qemu/bootstrap-hw.mk
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@ -6,7 +6,7 @@ SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/zynq/platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
NR_OF_CPUS = 1

6
repos/base-hw/src/lib/hw/spec/arm/arm_v6_cpu.cc → repos/base-hw/src/bootstrap/spec/arm/arm_v6_cpu.cc
View File

@ -13,11 +13,11 @@
* under the terms of the GNU Affero General Public License version 3.
*/
#include <hw/spec/arm/cpu.h>
#include <spec/arm/cpu.h>
void Hw::Arm_cpu::invalidate_data_cache() {
void Bootstrap::Cpu::invalidate_data_cache() {
asm volatile ("mcr p15, 0, %[rd], c7, c6, 0" :: [rd]"r"(0) : ); }
void Hw::Arm_cpu::clean_invalidate_data_cache() {
void Bootstrap::Cpu::clean_invalidate_data_cache() {
asm volatile ("mcr p15, 0, %[rd], c7, c14, 0" :: [rd]"r"(0) : ); }

6
repos/base-hw/src/lib/hw/spec/arm/arm_v7_cpu.cc → repos/base-hw/src/bootstrap/spec/arm/arm_v7_cpu.cc
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@ -12,7 +12,7 @@
* under the terms of the GNU Affero General Public License version 3.
*/
#include <hw/spec/arm/cpu.h>
#include <spec/arm/cpu.h>
/**
* Helpers that increase readability of MCR and MRC commands
@ -128,7 +128,7 @@
::: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9"
void Hw::Arm_cpu::invalidate_data_cache()
void Bootstrap::Cpu::invalidate_data_cache()
{
/**
* Data Cache Invalidate by Set/Way for all Set/Way
@ -139,7 +139,7 @@ void Hw::Arm_cpu::invalidate_data_cache()
}
void Hw::Arm_cpu::clean_invalidate_data_cache()
void Bootstrap::Cpu::clean_invalidate_data_cache()
{
/**
* Data Cache Clean by Set/Way for all Set/Way

3
repos/base-hw/src/bootstrap/spec/arm/cpu.h
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@ -55,6 +55,9 @@ struct Bootstrap::Cpu : Hw::Arm_cpu
static void wake_up_all_cpus(void * const ip);
static void enable_mmu_and_caches(Genode::addr_t table);
static void clean_invalidate_data_cache();
static void invalidate_data_cache();
};
#endif /* _SRC__BOOTSTRAP__SPEC__ARM__CPU_H_ */

14
repos/base-hw/src/core/spec/arm/cpu_support.h
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@ -83,22 +83,12 @@ struct Genode::Arm_cpu : public Hw::Arm_cpu
uint8_t id() { return cidr; }
};
/**
* Returns true if current execution context is running in user mode
*/
static bool is_user() { return Psr::M::get(Cpsr::read()) == Psr::M::USR; }
/**
* Invalidate all entries of all instruction caches
*/
static void invalidate_instr_cache() {
asm volatile ("mcr p15, 0, %0, c7, c5, 0" :: "r" (0) : ); }
/**
* Flush all entries of all data caches
*/
static void clean_invalidate_data_cache();
/**
* Invalidate all branch predictions
*/
@ -112,8 +102,8 @@ struct Genode::Arm_cpu : public Hw::Arm_cpu
* Clean and invalidate data-cache for virtual region
* 'base' - 'base + size'
*/
void clean_invalidate_data_cache_by_virt_region(addr_t base,
size_t const size)
static void clean_invalidate_data_cache_by_virt_region(addr_t base,
size_t const size)
{
addr_t const top = base + size;
base &= line_align_mask;

27
repos/base-hw/src/core/spec/arm/kernel/thread.cc
View File

@ -56,19 +56,6 @@ void Kernel::Thread::_call_update_data_region()
{
Cpu &cpu = cpu_pool().cpu(Cpu::executing_id());
/*
* FIXME: If the caller is not a core thread, the kernel operates in a
* different address space than the caller. Combined with the fact
* that at least ARMv7 doesn't provide cache operations by physical
* address, this prevents us from selectively maintaining caches.
* The future solution will be a kernel that is mapped to every
* address space so we can use virtual addresses of the caller. Up
* until then we apply operations to caches as a whole instead.
*/
if (!_core) {
cpu.clean_invalidate_data_cache();
return;
}
auto base = (addr_t)user_arg_1();
auto const size = (size_t)user_arg_2();
cpu.clean_invalidate_data_cache_by_virt_region(base, size);
@ -80,20 +67,6 @@ void Kernel::Thread::_call_update_instr_region()
{
Cpu &cpu = cpu_pool().cpu(Cpu::executing_id());
/*
* FIXME: If the caller is not a core thread, the kernel operates in a
* different address space than the caller. Combined with the fact
* that at least ARMv7 doesn't provide cache operations by physical
* address, this prevents us from selectively maintaining caches.
* The future solution will be a kernel that is mapped to every
* address space so we can use virtual addresses of the caller. Up
* until then we apply operations to caches as a whole instead.
*/
if (!_core) {
cpu.clean_invalidate_data_cache();
cpu.invalidate_instr_cache();
return;
}
auto base = (addr_t)user_arg_1();
auto const size = (size_t)user_arg_2();
cpu.clean_invalidate_data_cache_by_virt_region(base, size);

19
repos/base-hw/src/core/spec/arm_v6/cpu.cc
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@ -1,19 +0,0 @@
/*
* \brief CPU driver for core
* \author Norman Feske
* \author Martin stein
* \author Stefan Kalkowski
* \date 2012-08-30
*/
/*
* Copyright (C) 2012-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <spec/arm/cpu_support.h>
void Genode::Arm_cpu::clean_invalidate_data_cache() {
asm volatile ("mcr p15, 0, %[rd], c7, c14, 0" :: [rd]"r"(0) : ); }

3
repos/base-hw/src/core/spec/arm_v6/translation_table.h
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@ -26,8 +26,7 @@ constexpr bool Hw::Page_table::Descriptor_base::_smp() { return false; }
void Hw::Page_table::_translation_added(unsigned long addr, unsigned long size)
{
if (Genode::Arm_cpu::is_user()) Kernel::update_data_region(addr, size);
else Genode::Arm_cpu::clean_invalidate_data_cache();
Genode::Arm_cpu::clean_invalidate_data_cache_by_virt_region(addr, size);
}
#endif /* _CORE__SPEC__ARM_V6__TRANSLATION_TABLE_H_ */

150
repos/base-hw/src/core/spec/arm_v7/cpu.cc
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@ -1,150 +0,0 @@
/*
* \brief CPU driver for core
* \author Martin stein
* \author Stefan Kalkowski
* \date 2011-11-03
*/
/*
* Copyright (C) 2011-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <cpu.h>
/**
* Helpers that increase readability of MCR and MRC commands
*/
#define READ_CLIDR(rd) "mrc p15, 1, " #rd ", c0, c0, 1\n"
#define READ_CCSIDR(rd) "mrc p15, 1, " #rd ", c0, c0, 0\n"
#define WRITE_CSSELR(rs) "mcr p15, 2, " #rs ", c0, c0, 0\n"
#define WRITE_DCISW(rs) "mcr p15, 0, " #rs ", c7, c6, 2\n"
#define WRITE_DCCSW(rs) "mcr p15, 0, " #rs ", c7, c10, 2\n"
/**
* First macro to do a set/way operation on all entries of all data caches
*
* Must be inserted directly before the targeted operation. Returns operand
* for targeted operation in R6.
*/
#define FOR_ALL_SET_WAY_IN_R6_0 \
\
/* get the cache level value (Clidr::Loc) */ \
READ_CLIDR(r0) \
"ands r3, r0, #0x7000000\n" \
"mov r3, r3, lsr #23\n" \
\
/* skip all if cache level value is zero */ \
"beq 5f\n" \
"mov r9, #0\n" \
\
/* begin loop over cache numbers */ \
"1:\n" \
\
/* work out 3 x cache level */ \
"add r2, r9, r9, lsr #1\n" \
\
/* get the cache type of current cache number (Clidr::CtypeX) */ \
"mov r1, r0, lsr r2\n" \
"and r1, r1, #7\n" \
"cmp r1, #2\n" \
\
/* skip cache number if there's no data cache at this level */ \
"blt 4f\n" \
\
/* select the appropriate CCSIDR according to cache level and type */ \
WRITE_CSSELR(r9) \
"isb\n" \
\
/* get the line length of current cache (Ccsidr::LineSize) */ \
READ_CCSIDR(r1) \
"and r2, r1, #0x7\n" \
\
/* add 4 for the line-length offset (log2 of 16 bytes) */ \
"add r2, r2, #4\n" \
\
/* get the associativity or max way size (Ccsidr::Associativity) */ \
"ldr r4, =0x3ff\n" \
"ands r4, r4, r1, lsr #3\n" \
\
/* get the bit position of the way-size increment */ \
"clz r5, r4\n" \
\
/* get a working copy of the max way size */ \
"mov r8, r4\n" \
\
/* begin loop over way numbers */ \
"2:\n" \
\
/* get the number of sets or the max index size (Ccsidr::NumSets) */ \
"ldr r7, =0x00007fff\n" \
"ands r7, r7, r1, lsr #13\n" \
\
/* begin loop over indices */ \
"3:\n" \
\
/* factor in the way number and cache number into write value */ \
"orr r6, r9, r8, lsl r5\n" \
\
/* factor in the index number into write value */ \
"orr r6, r6, r7, lsl r2\n"
/**
* Second macro to do a set/way operation on all entries of all data caches
*
* Must be inserted directly after the targeted operation.
*/
#define FOR_ALL_SET_WAY_IN_R6_1 \
\
/* decrement the index */ \
"subs r7, r7, #1\n" \
\
/* end loop over indices */ \
"bge 3b\n" \
\
/* decrement the way number */ \
"subs r8, r8, #1\n" \
\
/* end loop over way numbers */ \
"bge 2b\n" \
\
/* label to skip a cache number */ \
"4:\n" \
\
/* increment the cache number */ \
"add r9, r9, #2\n" \
"cmp r3, r9\n" \
\
/* end loop over cache numbers */ \
"bgt 1b\n" \
\
/* synchronize data */ \
"dsb\n" \
\
/* label to skip all */ \
"5:\n" \
::: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9"
void Genode::Arm_v7_cpu::invalidate_inner_data_cache()
{
/**
* Data Cache Invalidate by Set/Way for all Set/Way
*/
asm volatile (FOR_ALL_SET_WAY_IN_R6_0
WRITE_DCISW(r6)
FOR_ALL_SET_WAY_IN_R6_1);
}
void Genode::Arm_v7_cpu::clean_invalidate_inner_data_cache()
{
/**
* Data Cache Clean by Set/Way for all Set/Way
*/
asm volatile (FOR_ALL_SET_WAY_IN_R6_0
WRITE_DCCSW(r6)
FOR_ALL_SET_WAY_IN_R6_1);
}

10
repos/base-hw/src/core/spec/arm_v7/cpu_support.h
View File

@ -31,16 +31,6 @@ struct Genode::Arm_v7_cpu : Arm_cpu
return mp;
}
/**
* Write back dirty lines of inner data cache and invalidate all
*/
static void clean_invalidate_inner_data_cache();
/**
* Invalidate all lines of the inner data cache
*/
static void invalidate_inner_data_cache();
/**
* Invalidate TLB for given address space id
*/

12
repos/base-hw/src/core/spec/cortex_a15/cpu.h
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@ -118,18 +118,6 @@ class Genode::Cpu : public Arm_v7_cpu
*/
static unsigned primary_id();
/**
* Write back dirty cache lines and invalidate all cache lines
*/
void clean_invalidate_data_cache() {
clean_invalidate_inner_data_cache(); }
/**
* Invalidate all cache lines
*/
void invalidate_data_cache() {
invalidate_inner_data_cache(); }
void switch_to(Context &, Mmu_context & mmu_context)
{
if (mmu_context.id() && (Ttbr0_64bit::read() != mmu_context.ttbr0))

6
repos/base-hw/src/core/spec/cortex_a8/cpu.cc
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@ -17,8 +17,8 @@
#include <kernel/cpu.h>
void Genode::Cpu::translation_added(Genode::addr_t const,
Genode::size_t const)
void Genode::Cpu::translation_added(Genode::addr_t const base,
Genode::size_t const size)
{
using namespace Kernel;
@ -29,5 +29,5 @@ void Genode::Cpu::translation_added(Genode::addr_t const,
* page table entry is added. We only do this as core as the kernel
* adds translations solely before MMU and caches are enabled.
*/
Cpu::clean_invalidate_data_cache();
Cpu::clean_invalidate_data_cache_by_virt_region(base, size);
}

12
repos/base-hw/src/core/spec/cortex_a8/cpu.h
View File

@ -23,18 +23,6 @@ namespace Genode { struct Cpu; }
struct Genode::Cpu : Arm_v7_cpu
{
/**
* Write back dirty cache lines and invalidate the whole cache
*/
static void clean_invalidate_data_cache() {
clean_invalidate_inner_data_cache(); }
/**
* Invalidate all cache lines
*/
static void invalidate_data_cache() {
invalidate_inner_data_cache(); }
/**
* Post processing after a translation was added to a translation table
*

3
repos/base-hw/src/core/spec/cortex_a8/translation_table.h
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@ -34,8 +34,7 @@ void Hw::Page_table::_translation_added(unsigned long addr, unsigned long size)
* page table entry is added. We only do this as core as the kernel
* adds translations solely before MMU and caches are enabled.
*/
if (Genode::Cpu::is_user()) Kernel::update_data_region(addr, size);
else Genode::Cpu::clean_invalidate_data_cache();
Genode::Cpu::clean_invalidate_data_cache_by_virt_region(addr, size);
}
#endif /* _CORE__SPEC__CORTEX_A8__TRANSLATION_TABLE_H_ */

18
repos/base-hw/src/core/spec/cortex_a9/cpu.h
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@ -23,24 +23,6 @@ namespace Genode { struct Cpu; }
struct Genode::Cpu : Arm_v7_cpu
{
/**
* Write back dirty cache lines and invalidate whole data cache
*/
void clean_invalidate_data_cache()
{
clean_invalidate_inner_data_cache();
Board::l2_cache().clean_invalidate();
}
/**
* Invalidate whole data cache
*/
void invalidate_data_cache()
{
invalidate_inner_data_cache();
Board::l2_cache().invalidate();
}
/**
* Clean and invalidate data-cache for virtual region
* 'base' - 'base + size'

3
repos/base-hw/src/lib/hw/spec/arm/cpu.h
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@ -260,9 +260,6 @@ struct Hw::Arm_cpu
** Cache maintainance functions **
**********************************/
static void clean_invalidate_data_cache();
static void invalidate_data_cache();
static inline void synchronization_barrier()
{
asm volatile("dsb\n"