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hw/x86: read out local APIC base dynamically 

Issue #2929
This commit is contained in:
Alexander Boettcher 2018-04-23 21:55:47 +02:00 committed by Christian Helmuth
parent a149131dc2
commit e6046e0bc1
6 changed files with 33 additions and 6 deletions
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3
repos/base-hw/src/bootstrap/spec/x86_64/platform.cc
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@ -27,8 +27,7 @@ extern "C" Genode::addr_t __initial_bx;
Bootstrap::Platform::Board::Board()
: core_mmio(Memory_region { 0, 0x1000 },
Memory_region { Hw::Cpu_memory_map::MMIO_LAPIC_BASE,
Hw::Cpu_memory_map::MMIO_LAPIC_SIZE },
Memory_region { Hw::Cpu_memory_map::lapic_phys_base(), 0x1000 },
Memory_region { Hw::Cpu_memory_map::MMIO_IOAPIC_BASE,
Hw::Cpu_memory_map::MMIO_IOAPIC_SIZE },
Memory_region { __initial_bx & ~0xFFFUL,

2
repos/base-hw/src/core/spec/x86_64/pic.cc
View File

@ -30,7 +30,7 @@ enum {
PIC_DATA_SLAVE = 0xa1,
};
Pic::Pic() : Mmio(Platform::mmio_to_virt(Hw::Cpu_memory_map::MMIO_LAPIC_BASE))
Pic::Pic() : Mmio(Platform::mmio_to_virt(Hw::Cpu_memory_map::lapic_phys_base()))
{
/* Start initialization sequence in cascade mode */
outb(PIC_CMD_MASTER, 0x11);

2
repos/base-hw/src/core/spec/x86_64/timer.cc
View File

@ -54,7 +54,7 @@ uint32_t Timer_driver::pit_calc_timer_freq(void)
Timer_driver::Timer_driver(unsigned)
: Mmio(Platform::mmio_to_virt(Hw::Cpu_memory_map::MMIO_LAPIC_BASE))
: Mmio(Platform::mmio_to_virt(Hw::Cpu_memory_map::lapic_phys_base()))
{
/* Enable LAPIC timer in one-shot mode */
write<Tmr_lvt::Vector>(Board::TIMER_VECTOR_KERNEL);

6
repos/base-hw/src/lib/hw/spec/x86_64/cpu.h
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@ -78,6 +78,12 @@ struct Hw::X86_64_cpu
struct Smep : Bitfield<20, 1> { }; /* SMEP Enable */
struct Smap : Bitfield<21, 1> { }; /* SMAP Enable */
);
X86_64_MSR_REGISTER(IA32_apic_base, 0x1b,
struct Bsp : Bitfield< 8, 1> { }; /* Bootstrap processor */
struct Lapic : Bitfield< 11, 1> { }; /* Enable/disable local APIC */
struct Base : Bitfield< 12, 24> { }; /* Base address of APIC registers */
);
};
#endif /* _SRC__LIB__HW__SPEC__X86_64__CPU_H_ */

16
repos/base-hw/src/lib/hw/spec/x86_64/register_macros.h
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@ -32,4 +32,20 @@
__VA_ARGS__; \
};
#define X86_64_MSR_REGISTER(name, msr, ...) \
struct name : Genode::Register<64> \
{ \
static access_t read() \
{ \
access_t low; \
access_t high; \
asm volatile ("rdmsr" : "=a" (low), "=d" (high) : "c" (msr)); \
return (high << 32) | (low & ~0U); \
} \
\
static void write(access_t const) { } \
\
__VA_ARGS__; \
};
#endif /* _SRC__LIB__HW__SPEC__X86_64__REGISTER_MACROS_H_ */

10
repos/base-hw/src/lib/hw/spec/x86_64/x86_64.h
View File

@ -15,6 +15,7 @@
#define _SRC__LIB__HW__SPEC__X86_64__X86_64_H_
#include <base/stdint.h>
#include <hw/spec/x86_64/cpu.h>
namespace Hw { struct Cpu_memory_map; }
@ -22,11 +23,16 @@ namespace Hw { struct Cpu_memory_map; }
struct Hw::Cpu_memory_map
{
enum {
MMIO_LAPIC_BASE = 0xfee00000,
MMIO_LAPIC_SIZE = 0x1000,
MMIO_IOAPIC_BASE = 0xfec00000,
MMIO_IOAPIC_SIZE = 0x1000,
};
static Genode::addr_t lapic_phys_base()
{
Hw::X86_64_cpu::IA32_apic_base::access_t msr_apic_base;
msr_apic_base = Hw::X86_64_cpu::IA32_apic_base::read();
return Hw::X86_64_cpu::IA32_apic_base::Base::masked(msr_apic_base);
}
};
#endif /* _SRC__LIB__HW__SPEC__X86_64__X86_64_H_ */