From e17accb3ba2cdf43df547edf67e54b90cc8cc8a1 Mon Sep 17 00:00:00 2001 From: Sebastian Sumpf Date: Thu, 24 Aug 2017 16:22:02 +0200 Subject: [PATCH] base-hw: RISC-V save/restore 'x29' correctly * register x29/t4 was not saved and therefore not restored correctly * change 'warning' to 'error' before '_die' is called issue #2423 --- repos/base-hw/src/core/spec/riscv/exception_vector.s | 5 +++-- repos/base-hw/src/core/spec/riscv/kernel/thread.cc | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/repos/base-hw/src/core/spec/riscv/exception_vector.s b/repos/base-hw/src/core/spec/riscv/exception_vector.s index feb0d47e7..5ddea40b4 100644 --- a/repos/base-hw/src/core/spec/riscv/exception_vector.s +++ b/repos/base-hw/src/core/spec/riscv/exception_vector.s @@ -61,7 +61,8 @@ _mt_kernel_entry_pic: addi x31, x31, 8 # save x30 in master - sd x30, CPU_X1 + 8 * 28(x31) + sd x29, CPU_X1 + 8 * 28(x31) + sd x30, CPU_X1 + 8 * 29(x31) # load kernel page table ld x30, CPU_SPTBR(x31) @@ -149,7 +150,7 @@ _mt_user_entry_pic: sfence.vm x0 - # restore x29 - x31 from master context + # restore x29 - x31 from master context .irp reg,31,30,29 ld x\reg, CPU_X1 + 8 * (\reg - 1)(x29) .endr diff --git a/repos/base-hw/src/core/spec/riscv/kernel/thread.cc b/repos/base-hw/src/core/spec/riscv/kernel/thread.cc index 0534a4840..ed6bb0557 100644 --- a/repos/base-hw/src/core/spec/riscv/kernel/thread.cc +++ b/repos/base-hw/src/core/spec/riscv/kernel/thread.cc @@ -35,8 +35,8 @@ void Thread::exception(unsigned const cpu) _mmu_exception(); break; default: - Genode::warning(*this, ": unhandled exception ", cpu_exception, - " at ip=", (void*)ip, " addr=", Cpu::sbadaddr()); + Genode::error(*this, ": unhandled exception ", cpu_exception, + " at ip=", (void*)ip, " addr=", Genode::Hex(Cpu::sbadaddr())); _die(); } }