diff --git a/repos/base-hw/lib/mk/arm_v6/core.inc b/repos/base-hw/lib/mk/arm_v6/core.inc index b3dd54d91..e517e445a 100644 --- a/repos/base-hw/lib/mk/arm_v6/core.inc +++ b/repos/base-hw/lib/mk/arm_v6/core.inc @@ -7,6 +7,9 @@ # add include paths INC_DIR += $(REP_DIR)/src/core/include/spec/arm_v6 +# add C++ sources +SRC_CC += cpu.cc + # add assembly sources SRC_S += spec/arm_v6/mode_transition.s diff --git a/repos/base-hw/lib/mk/exynos5/core.inc b/repos/base-hw/lib/mk/exynos5/core.inc index 0b6c056cc..32fc59454 100644 --- a/repos/base-hw/lib/mk/exynos5/core.inc +++ b/repos/base-hw/lib/mk/exynos5/core.inc @@ -6,6 +6,7 @@ # add include paths INC_DIR += $(REP_DIR)/src/core/include/spec/exynos5 +INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a15 INC_DIR += $(REP_DIR)/src/core/include/spec/corelink_gic400 # add C++ sources diff --git a/repos/base-hw/lib/mk/platform_arndale/core.mk b/repos/base-hw/lib/mk/platform_arndale/core.mk index de38864cf..1e5f67cf4 100644 --- a/repos/base-hw/lib/mk/platform_arndale/core.mk +++ b/repos/base-hw/lib/mk/platform_arndale/core.mk @@ -10,6 +10,7 @@ INC_DIR += $(REP_DIR)/src/core/include/spec/arndale # add C++ sources SRC_CC += spec/arndale/platform_support.cc +SRC_CC += spec/arndale/cpu.cc # include less specific configuration include $(REP_DIR)/lib/mk/exynos5/core.inc diff --git a/repos/base-hw/lib/mk/platform_imx53/core.mk b/repos/base-hw/lib/mk/platform_imx53/core.mk index 6e198d3ad..142fe640b 100644 --- a/repos/base-hw/lib/mk/platform_imx53/core.mk +++ b/repos/base-hw/lib/mk/platform_imx53/core.mk @@ -13,5 +13,8 @@ INC_DIR += $(REP_DIR)/src/core/include/spec/imx53 INC_DIR += $(REP_DIR)/src/core/include/spec/imx INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a8 +# add C++ sources +SRC_CC += cpu.cc + # include less specific configuration include $(REP_DIR)/lib/mk/arm_v7/core.inc diff --git a/repos/base-hw/lib/mk/platform_odroid_xu/core.mk b/repos/base-hw/lib/mk/platform_odroid_xu/core.mk index ed45d5ebf..47d00a531 100644 --- a/repos/base-hw/lib/mk/platform_odroid_xu/core.mk +++ b/repos/base-hw/lib/mk/platform_odroid_xu/core.mk @@ -9,6 +9,7 @@ INC_DIR += $(REP_DIR)/src/core/include/spec/odroid_xu # add C++ sources SRC_CC += spec/odroid_xu/platform_support.cc +SRC_CC += cpu.cc # include less specific library parts include $(REP_DIR)/lib/mk/exynos5/core.inc diff --git a/repos/base-hw/lib/mk/platform_panda/core.mk b/repos/base-hw/lib/mk/platform_panda/core.mk index 6d7564979..0566160b0 100644 --- a/repos/base-hw/lib/mk/platform_panda/core.mk +++ b/repos/base-hw/lib/mk/platform_panda/core.mk @@ -15,6 +15,7 @@ SRC_CC += platform_services.cc SRC_CC += spec/panda/platform_support.cc SRC_CC += spec/cortex_a9/pic.cc SRC_CC += spec/arm_gic/pic.cc +SRC_CC += cpu.cc # include less specific configuration include $(REP_DIR)/lib/mk/arm_v7/core.inc diff --git a/repos/base-hw/lib/mk/platform_pbxa9/core.mk b/repos/base-hw/lib/mk/platform_pbxa9/core.mk index 27dfde35f..b42dd1aaf 100644 --- a/repos/base-hw/lib/mk/platform_pbxa9/core.mk +++ b/repos/base-hw/lib/mk/platform_pbxa9/core.mk @@ -15,6 +15,7 @@ SRC_CC += platform_services.cc SRC_CC += spec/pbxa9/platform_support.cc SRC_CC += spec/cortex_a9/pic.cc SRC_CC += spec/arm_gic/pic.cc +SRC_CC += cpu.cc # include less specific configuration include $(REP_DIR)/lib/mk/arm_v7/core.inc diff --git a/repos/base-hw/lib/mk/platform_vea9x4/core.mk b/repos/base-hw/lib/mk/platform_vea9x4/core.mk index fa1420255..3ad2a5697 100644 --- a/repos/base-hw/lib/mk/platform_vea9x4/core.mk +++ b/repos/base-hw/lib/mk/platform_vea9x4/core.mk @@ -13,5 +13,8 @@ INC_DIR += $(REP_DIR)/src/core/include/spec/vea9x4 INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a9 INC_DIR += $(REP_DIR)/src/core/include/spec/pl011 +# add C++ sources +SRC_CC += cpu.cc + # include less specific configuration include $(REP_DIR)/lib/mk/arm_v7/core.inc diff --git a/repos/base-hw/src/core/cpu.cc b/repos/base-hw/src/core/cpu.cc new file mode 100644 index 000000000..74a017918 --- /dev/null +++ b/repos/base-hw/src/core/cpu.cc @@ -0,0 +1,21 @@ +/* + * \brief CPU driver for core + * \author Martin stein + * \date 2014-07-14 + */ + +/* + * Copyright (C) 2011-2014 Genode Labs GmbH + * + * This file is part of the Genode OS framework, which is distributed + * under the terms of the GNU General Public License version 2. + */ + +/* core includes */ +#include + +using namespace Genode; + +unsigned Cpu::primary_id() { return 0; } + +unsigned Cpu::executing_id() { return primary_id(); } diff --git a/repos/base-hw/src/core/include/kernel/processor.h b/repos/base-hw/src/core/include/kernel/processor.h index 1454d8900..d99adfd79 100644 --- a/repos/base-hw/src/core/include/kernel/processor.h +++ b/repos/base-hw/src/core/include/kernel/processor.h @@ -17,14 +17,11 @@ /* core includes */ #include -#include +#include #include namespace Kernel { - using Genode::Processor_driver; - using Genode::Processor_lazy_state; - /** * A single user of a multiplexable processor */ @@ -60,10 +57,7 @@ class Kernel::Processor_domain_update /** * Domain-update back-end */ - void _domain_update() - { - Processor_driver::flush_tlb_by_pid(_domain_id); - } + void _domain_update() { Cpu::flush_tlb_by_pid(_domain_id); } /** * Perform the domain update on the executing processors @@ -99,8 +93,8 @@ class Kernel::Processor_client : public Processor_scheduler::Item { protected: - Processor * _processor; - Processor_lazy_state _lazy_state; + Processor * _processor; + Cpu_lazy_state _lazy_state; /** * Handle an interrupt exception that occured during execution @@ -166,10 +160,10 @@ class Kernel::Processor_client : public Processor_scheduler::Item ** Accessors ** ***************/ - Processor_lazy_state * lazy_state() { return &_lazy_state; } + Cpu_lazy_state * lazy_state() { return &_lazy_state; } }; -class Kernel::Processor : public Processor_driver +class Kernel::Processor : public Cpu { private: @@ -252,7 +246,7 @@ class Kernel::Processor : public Processor_driver * an occupant other than that whose exception caused the kernel entry. */ Processor_client * const old_client = _scheduler.occupant(); - Processor_lazy_state * const old_state = old_client->lazy_state(); + Cpu_lazy_state * const old_state = old_client->lazy_state(); old_client->exception(_id); /* @@ -263,7 +257,7 @@ class Kernel::Processor : public Processor_driver bool update; Processor_client * const new_client = _scheduler.update_occupant(update); if (update) { _reset_timer(); } - Processor_lazy_state * const new_state = new_client->lazy_state(); + Cpu_lazy_state * const new_state = new_client->lazy_state(); prepare_proceeding(old_state, new_state); new_client->proceed(_id); } diff --git a/repos/base-hw/src/core/include/kernel/processor_pool.h b/repos/base-hw/src/core/include/kernel/processor_pool.h index 16198a18f..61180d0fa 100644 --- a/repos/base-hw/src/core/include/kernel/processor_pool.h +++ b/repos/base-hw/src/core/include/kernel/processor_pool.h @@ -46,7 +46,7 @@ class Kernel::Idle_thread : public Thread enum { STACK_SIZE = sizeof(addr_t) * 32, - STACK_ALIGNM = Processor_driver::DATA_ACCESS_ALIGNM, + STACK_ALIGNM = Cpu::DATA_ACCESS_ALIGNM, }; char _stack[STACK_SIZE] __attribute__((aligned(STACK_ALIGNM))); @@ -54,10 +54,7 @@ class Kernel::Idle_thread : public Thread /** * Main function of all idle threads */ - static void _main() - { - while (1) { Processor_driver::wait_for_interrupt(); } - } + static void _main() { while (1) { Cpu::wait_for_interrupt(); } } public: diff --git a/repos/base-hw/src/core/include/kernel/thread.h b/repos/base-hw/src/core/include/kernel/thread.h index 46b654b25..3ff0d159b 100644 --- a/repos/base-hw/src/core/include/kernel/thread.h +++ b/repos/base-hw/src/core/include/kernel/thread.h @@ -46,7 +46,7 @@ namespace Kernel } -struct Kernel::Cpu_context : Processor_driver::Context +struct Kernel::Cpu_context : Cpu::Context { private: @@ -68,7 +68,7 @@ struct Kernel::Cpu_context : Processor_driver::Context class Kernel::Thread : - public Processor_driver::User_context, + public Cpu::User_context, public Object, public Processor_client, public Processor_domain_update, diff --git a/repos/base-hw/src/core/include/spec/arm/processor_driver_support.h b/repos/base-hw/src/core/include/spec/arm/cpu_support.h similarity index 98% rename from repos/base-hw/src/core/include/spec/arm/processor_driver_support.h rename to repos/base-hw/src/core/include/spec/arm/cpu_support.h index a9444a3f2..556ca0c14 100644 --- a/repos/base-hw/src/core/include/spec/arm/processor_driver_support.h +++ b/repos/base-hw/src/core/include/spec/arm/cpu_support.h @@ -12,8 +12,8 @@ * under the terms of the GNU General Public License version 2. */ -#ifndef _SPEC__ARM__PROCESSOR_DRIVER_SUPPORT_H_ -#define _SPEC__ARM__PROCESSOR_DRIVER_SUPPORT_H_ +#ifndef _SPEC__ARM__CPU_SUPPORT_H_ +#define _SPEC__ARM__CPU_SUPPORT_H_ /* Genode includes */ #include @@ -635,10 +635,8 @@ class Genode::Arm * Invalidate all entries of all instruction caches */ __attribute__((always_inline)) - static void invalidate_instr_caches() - { - asm volatile ("mcr p15, 0, %[rd], c7, c5, 0" :: [rd]"r"(0) : ); - } + static void invalidate_instr_caches() { + asm volatile ("mcr p15, 0, %[rd], c7, c5, 0" :: [rd]"r"(0) : ); } /** * Flush all entries of all data caches @@ -715,4 +713,4 @@ class Genode::Arm static bool is_smp() { return PROCESSORS > 1; } }; -#endif /* _SPEC__ARM__PROCESSOR_DRIVER_SUPPORT_H_ */ +#endif /* _SPEC__ARM__CPU_SUPPORT_H_ */ diff --git a/repos/base-hw/src/core/include/spec/arm/short_translation_table.h b/repos/base-hw/src/core/include/spec/arm/short_translation_table.h index eda03ac7d..5334f05a0 100644 --- a/repos/base-hw/src/core/include/spec/arm/short_translation_table.h +++ b/repos/base-hw/src/core/include/spec/arm/short_translation_table.h @@ -22,7 +22,7 @@ /* base-hw includes */ #include #include -#include +#include namespace Genode { @@ -183,7 +183,7 @@ class Genode::Translation_table access_t v = access_permission_bits(flags); v |= arm_memory_region_attr(flags); v |= Ng::bits(!flags.global); - v |= S::bits(Processor_driver::is_smp()); + v |= S::bits(Cpu::is_smp()); v |= Pa::masked(pa); Descriptor::type(v, Descriptor::SMALL_PAGE); return v; @@ -272,7 +272,6 @@ class Genode::Translation_table _entries[i] = Small_page::create(flags, pa); /* some processors need to act on changed translations */ - using Cpu = Genode::Processor_driver; Cpu::translation_added((addr_t)&_entries[i], sizeof(Descriptor::access_t)); } @@ -451,7 +450,7 @@ class Genode::Translation_table access_t v = access_permission_bits
(flags); v |= arm_memory_region_attr
(flags); v |= Domain::bits(DOMAIN); - v |= S::bits(Processor_driver::is_smp()); + v |= S::bits(Cpu::is_smp()); v |= Ng::bits(!flags.global); v |= Pa::masked(pa); Descriptor::type(v, Descriptor::SECTION); @@ -515,7 +514,6 @@ class Genode::Translation_table _entries[i] = Page_table_descriptor::create(pt_phys); /* some processors need to act on changed translations */ - using Cpu = Genode::Processor_driver; Cpu::translation_added((addr_t)&_entries[i], sizeof(Descriptor::access_t)); } @@ -607,7 +605,6 @@ class Genode::Translation_table _entries[i] = Section::create(flags, pa); /* some processors need to act on changed translations */ - using Cpu = Genode::Processor_driver; Cpu::translation_added((addr_t)&_entries[i], sizeof(Descriptor::access_t)); break; diff --git a/repos/base-hw/src/core/include/spec/arm_gic/pic_support.h b/repos/base-hw/src/core/include/spec/arm_gic/pic_support.h index e63aa5d01..578c8f26e 100644 --- a/repos/base-hw/src/core/include/spec/arm_gic/pic_support.h +++ b/repos/base-hw/src/core/include/spec/arm_gic/pic_support.h @@ -19,18 +19,195 @@ namespace Genode { + /** + * Disributor of the ARM generic interrupt controller + */ + class Arm_gic_distributor; + + /** + * CPU interface of the ARM generic interrupt controller + */ + class Arm_gic_cpu_interface; + /** * Programmable interrupt controller for core */ class Arm_gic; } -class Genode::Arm_gic +class Genode::Arm_gic_distributor : public Mmio { public: enum { NR_OF_IRQ = 1024 }; + /** + * Constructor + */ + Arm_gic_distributor(addr_t const base) : Mmio(base) { } + + /** + * Control register + */ + struct Ctlr : Register<0x000, 32> + { + struct Enable : Bitfield<0,1> { }; + }; + + /** + * Controller type register + */ + struct Typer : Register<0x004, 32> + { + struct It_lines_number : Bitfield<0,5> { }; + struct Cpu_number : Bitfield<5,3> { }; + }; + + /** + * Interrupt group register + */ + struct Igroupr : Register_array<0x80, 32, NR_OF_IRQ, 1> + { + struct Group_status : Bitfield<0, 1> { }; + }; + + /** + * Interrupt set enable registers + */ + struct Isenabler : Register_array<0x100, 32, NR_OF_IRQ, 1, true> + { + struct Set_enable : Bitfield<0, 1> { }; + }; + + /** + * Interrupt clear enable registers + */ + struct Icenabler : Register_array<0x180, 32, NR_OF_IRQ, 1, true> + { + struct Clear_enable : Bitfield<0, 1> { }; + }; + + /** + * Interrupt priority level registers + */ + struct Ipriorityr : Register_array<0x400, 32, NR_OF_IRQ, 8> + { + enum { GET_MIN = 0xff }; + + struct Priority : Bitfield<0, 8> { }; + }; + + /** + * Interrupt processor target registers + */ + struct Itargetsr : Register_array<0x800, 32, NR_OF_IRQ, 8> + { + struct Cpu_targets : Bitfield<0, 8> { }; + }; + + /** + * Interrupt configuration registers + */ + struct Icfgr : Register_array<0xc00, 32, NR_OF_IRQ, 2> + { + struct Edge_triggered : Bitfield<1, 1> { }; + }; + + /** + * Software generated interrupt register + */ + struct Sgir : Register<0xf00, 32> + { + struct Sgi_int_id : Bitfield<0, 4> { }; + struct Cpu_target_list : Bitfield<16, 8> { }; + }; + + /** + * Minimum supported interrupt priority + */ + Ipriorityr::access_t min_priority() + { + write(Ipriorityr::GET_MIN, 0); + return read(0); + } + + /** + * Maximum supported interrupt priority + */ + Ipriorityr::access_t max_priority() { return 0; } + + /** + * ID of the maximum supported interrupt + */ + Typer::access_t max_interrupt() + { + enum { LINE_WIDTH_LOG2 = 5 }; + Typer::access_t lnr = read(); + return ((lnr + 1) << LINE_WIDTH_LOG2) - 1; + } +}; + +class Genode::Arm_gic_cpu_interface : public Mmio +{ + public: + + /** + * Constructor + */ + Arm_gic_cpu_interface(addr_t const base) : Mmio(base) { } + + /** + * Control register + */ + struct Ctlr : Register<0x00, 32> + { + /* Without security extension */ + struct Enable : Bitfield<0,1> { }; + + /* In a secure world */ + struct Enable_grp0 : Bitfield<0,1> { }; + struct Enable_grp1 : Bitfield<1,1> { }; + struct Fiq_en : Bitfield<3,1> { }; + }; + + /** + * Priority mask register + */ + struct Pmr : Register<0x04, 32> + { + struct Priority : Bitfield<0,8> { }; + }; + + /** + * Binary point register + */ + struct Bpr : Register<0x08, 32> + { + enum { NO_PREEMPTION = 7 }; + + struct Binary_point : Bitfield<0,3> { }; + }; + + /** + * Interrupt acknowledge register + */ + struct Iar : Register<0x0c, 32, true> + { + struct Irq_id : Bitfield<0,10> { }; + }; + + /** + * End of interrupt register + */ + struct Eoir : Register<0x10, 32, true> + { + struct Irq_id : Bitfield<0,10> { }; + struct Cpu_id : Bitfield<10,3> { }; + }; +}; + +class Genode::Arm_gic +{ protected: enum { @@ -38,186 +215,11 @@ class Genode::Arm_gic SPURIOUS_ID = 1023, }; - /** - * Distributor interface - */ - struct Distr : public Mmio - { - /** - * Constructor - */ - Distr(addr_t const base) : Mmio(base) { } - - /** - * Control register - */ - struct Ctlr : Register<0x000, 32> - { - struct Enable : Bitfield<0,1> { }; - }; - - /** - * Controller type register - */ - struct Typer : Register<0x004, 32> - { - struct It_lines_number : Bitfield<0,5> { }; - struct Cpu_number : Bitfield<5,3> { }; - }; - - /** - * Interrupt group register - */ - struct Igroupr : - Register_array<0x80, 32, NR_OF_IRQ, 1> - { - struct Group_status : Bitfield<0, 1> { }; - }; - - /** - * Interrupt set enable registers - */ - struct Isenabler : - Register_array<0x100, 32, NR_OF_IRQ, 1, true> - { - struct Set_enable : Bitfield<0, 1> { }; - }; - - /** - * Interrupt clear enable registers - */ - struct Icenabler : - Register_array<0x180, 32, NR_OF_IRQ, 1, true> - { - struct Clear_enable : Bitfield<0, 1> { }; - }; - - /** - * Interrupt priority level registers - */ - struct Ipriorityr : - Register_array<0x400, 32, NR_OF_IRQ, 8> - { - enum { GET_MIN = 0xff }; - - struct Priority : Bitfield<0, 8> { }; - }; - - /** - * Interrupt processor target registers - */ - struct Itargetsr : - Register_array<0x800, 32, NR_OF_IRQ, 8> - { - enum { ALL = 0xff }; - - struct Cpu_targets : Bitfield<0, 8> { }; - }; - - /** - * Interrupt configuration registers - */ - struct Icfgr : - Register_array<0xc00, 32, NR_OF_IRQ, 2> - { - struct Edge_triggered : Bitfield<1, 1> { }; - }; - - /** - * Software generated interrupt register - */ - struct Sgir : Register<0xf00, 32> - { - struct Sgi_int_id : Bitfield<0, 4> { }; - struct Cpu_target_list : Bitfield<16, 8> { }; - }; - - /** - * Minimum supported interrupt priority - */ - Ipriorityr::access_t min_priority() - { - write(Ipriorityr::GET_MIN, 0); - return read(0); - } - - /** - * Maximum supported interrupt priority - */ - Ipriorityr::access_t max_priority() { return 0; } - - /** - * ID of the maximum supported interrupt - */ - Typer::access_t max_interrupt() - { - enum { LINE_WIDTH_LOG2 = 5 }; - Typer::access_t lnr = read(); - return ((lnr + 1) << LINE_WIDTH_LOG2) - 1; - } - - } _distr; - - /** - * CPU interface - */ - struct Cpu : public Mmio - { - /** - * Constructor - */ - Cpu(addr_t const base) : Mmio(base) { } - - /** - * Control register - */ - struct Ctlr : Register<0x00, 32> - { - /* Without security extension */ - struct Enable : Bitfield<0,1> { }; - - /* In a secure world */ - struct Enable_grp0 : Bitfield<0,1> { }; - struct Enable_grp1 : Bitfield<1,1> { }; - struct Fiq_en : Bitfield<3,1> { }; - }; - - /** - * Priority mask register - */ - struct Pmr : Register<0x04, 32> - { - struct Priority : Bitfield<0,8> { }; - }; - - /** - * Binary point register - */ - struct Bpr : Register<0x08, 32> - { - enum { NO_PREEMPTION = 7 }; - - struct Binary_point : Bitfield<0,3> { }; - }; - - /** - * Interrupt acknowledge register - */ - struct Iar : Register<0x0c, 32, true> - { - struct Irq_id : Bitfield<0,10> { }; - }; - - /** - * End of interrupt register - */ - struct Eoir : Register<0x10, 32, true> - { - struct Irq_id : Bitfield<0,10> { }; - struct Cpu_id : Bitfield<10,3> { }; - }; - } _cpu; + typedef Arm_gic_cpu_interface Cpui; + typedef Arm_gic_distributor Distr; + Distr _distr; + Cpui _cpui; unsigned const _max_interrupt; unsigned _last_request; @@ -238,12 +240,14 @@ class Genode::Arm_gic public: + enum { NR_OF_IRQ = Distr::NR_OF_IRQ }; + /** * Constructor */ Arm_gic(addr_t const distr_base, addr_t const cpu_base) : - _distr(distr_base), _cpu(cpu_base), + _distr(distr_base), _cpui(cpu_base), _max_interrupt(_distr.max_interrupt()), _last_request(SPURIOUS_ID) { @@ -256,13 +260,13 @@ class Genode::Arm_gic void init_processor_local() { /* disable the priority filter */ - _cpu.write(_distr.min_priority()); + _cpui.write(_distr.min_priority()); /* disable preemption of interrupt handling by interrupts */ - _cpu.write(Cpu::Bpr::NO_PREEMPTION); + _cpui.write(Cpui::Bpr::NO_PREEMPTION); /* enable device */ - _cpu.write(1); + _cpui.write(1); } /** @@ -275,7 +279,7 @@ class Genode::Arm_gic */ bool take_request(unsigned & i) { - _last_request = _cpu.read(); + _last_request = _cpui.read(); i = _last_request; return valid(i); } @@ -286,8 +290,8 @@ class Genode::Arm_gic void finish_request() { if (!valid(_last_request)) return; - _cpu.write(Cpu::Eoir::Irq_id::bits(_last_request) | - Cpu::Eoir::Cpu_id::bits(0) ); + _cpui.write(Cpui::Eoir::Irq_id::bits(_last_request) | + Cpui::Eoir::Cpu_id::bits(0) ); _last_request = SPURIOUS_ID; } diff --git a/repos/base-hw/src/core/include/spec/arm_v6/processor_driver.h b/repos/base-hw/src/core/include/spec/arm_v6/cpu.h similarity index 79% rename from repos/base-hw/src/core/include/spec/arm_v6/processor_driver.h rename to repos/base-hw/src/core/include/spec/arm_v6/cpu.h index d15e0e6a8..9d86cc81f 100644 --- a/repos/base-hw/src/core/include/spec/arm_v6/processor_driver.h +++ b/repos/base-hw/src/core/include/spec/arm_v6/cpu.h @@ -1,5 +1,5 @@ /* - * \brief Processor driver for core + * \brief CPU driver for core * \author Norman Feske * \author Martin stein * \date 2012-08-30 @@ -12,28 +12,34 @@ * under the terms of the GNU General Public License version 2. */ -#ifndef _PROCESSOR_DRIVER_H_ -#define _PROCESSOR_DRIVER_H_ +#ifndef _CPU_H_ +#define _CPU_H_ /* core includes */ -#include +#include #include #include namespace Genode { /** - * Part of processor state that is not switched on every mode transition + * Part of CPU state that is not switched on every mode transition */ - class Processor_lazy_state { }; + class Cpu_lazy_state { }; /** - * Processor driver for core + * CPU driver for core */ - class Processor_driver; + class Cpu; } -class Genode::Processor_driver : public Arm +namespace Kernel +{ + using Genode::Cpu_lazy_state; + using Genode::Cpu; +} + +class Genode::Cpu : public Arm { public: @@ -178,56 +184,12 @@ class Genode::Processor_driver : public Arm */ static void tlb_insertions() { flush_tlb(); } - static void start_secondary_processors(void * const ip) - { - assert(!is_smp()); - } - - /** - * Invalidate all predictions about the future control-flow - */ - static void invalidate_control_flow_predictions() - { - /* FIXME invalidation of branch prediction not implemented */ - } - - /** - * Finish all previous data transfers - */ - static void data_synchronization_barrier() - { - /* FIXME data synchronization barrier not implemented */ - } - - /** - * Wait for the next interrupt as cheap as possible - */ - static void wait_for_interrupt() - { - /* FIXME cheap way of waiting is not implemented */ - } - - /** - * Return kernel name of the primary processor - */ - static unsigned primary_id() { return 0; } - - /** - * Return kernel name of the executing processor - */ - static unsigned executing_id() { return primary_id(); } - - - /** - * Prepare for the proceeding of a user - */ - static void prepare_proceeding(Processor_lazy_state *, - Processor_lazy_state *) { } + static void start_secondary_processors(void *) { assert(!is_smp()); } /** * Return wether to retry an undefined user instruction after this call */ - bool retry_undefined_instr(Processor_lazy_state *) { return false; } + bool retry_undefined_instr(Cpu_lazy_state *) { return false; } /** * Post processing after a translation was added to a translation table @@ -246,6 +208,25 @@ class Genode::Processor_driver : public Arm */ if (is_user()) Kernel::update_data_region(addr, size); } + + /** + * Return kernel name of the executing processor + */ + static unsigned executing_id(); + + /** + * Return kernel name of the primary processor + */ + static unsigned primary_id(); + + /************* + ** Dummies ** + *************/ + + static void prepare_proceeding(Cpu_lazy_state *, Cpu_lazy_state *) { } + static void wait_for_interrupt() { /* FIXME */ } + static void data_synchronization_barrier() { /* FIXME */ } + static void invalidate_control_flow_predictions() { /* FIXME */ } }; @@ -260,5 +241,4 @@ void Genode::Arm::invalidate_data_caches() asm volatile ("mcr p15, 0, %[rd], c7, c6, 0" :: [rd]"r"(0) : ); } - -#endif /* _PROCESSOR_DRIVER_H_ */ +#endif /* _CPU_H_ */ diff --git a/repos/base-hw/src/core/include/spec/arm_v7/processor_driver_support.h b/repos/base-hw/src/core/include/spec/arm_v7/cpu_support.h similarity index 97% rename from repos/base-hw/src/core/include/spec/arm_v7/processor_driver_support.h rename to repos/base-hw/src/core/include/spec/arm_v7/cpu_support.h index 79b23bec3..97956519f 100644 --- a/repos/base-hw/src/core/include/spec/arm_v7/processor_driver_support.h +++ b/repos/base-hw/src/core/include/spec/arm_v7/cpu_support.h @@ -11,11 +11,11 @@ * under the terms of the GNU General Public License version 2. */ -#ifndef _SPEC__ARM_V7__PROCESSOR_DRIVER_SUPPORT_H_ -#define _SPEC__ARM_V7__PROCESSOR_DRIVER_SUPPORT_H_ +#ifndef _SPEC__ARM_V7__CPU_SUPPORT_H_ +#define _SPEC__ARM_V7__CPU_SUPPORT_H_ /* core includes */ -#include +#include #include /** @@ -411,5 +411,5 @@ Genode::Arm::Psr::init_user_with_trustzone() } -#endif /* _SPEC__ARM_V7__PROCESSOR_DRIVER_SUPPORT_H_ */ +#endif /* _SPEC__ARM_V7__CPU_SUPPORT_H_ */ diff --git a/repos/base-hw/src/core/include/spec/arndale/processor_driver.h b/repos/base-hw/src/core/include/spec/arndale/processor_driver.h deleted file mode 100644 index 73c8f0634..000000000 --- a/repos/base-hw/src/core/include/spec/arndale/processor_driver.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * \brief Processor driver for core - * \author Martin Stein - * \date 2012-04-23 - */ - -/* - * Copyright (C) 2012 Genode Labs GmbH - * - * This file is part of the Genode OS framework, which is distributed - * under the terms of the GNU General Public License version 2. - */ - -#ifndef _PROCESSOR_DRIVER_H_ -#define _PROCESSOR_DRIVER_H_ - -/* core includes */ -#include - -namespace Genode -{ - /** - * Processor driver for core - */ - class Processor_driver : public Cortex_a15 - { - public: - - /** - * Return kernel name of the executing processor - */ - static unsigned executing_id() - { - return Mpidr::Aff_0::get(Mpidr::read()); - } - - /** - * Return kernel name of the primary processor - */ - static unsigned primary_id() { return Board::PRIMARY_MPIDR_AFF_0; } - }; -} - -#endif /* _PROCESSOR_DRIVER_H_ */ diff --git a/repos/base-hw/src/core/include/spec/cortex_a15/cpu.h b/repos/base-hw/src/core/include/spec/cortex_a15/cpu.h new file mode 100644 index 000000000..05163738f --- /dev/null +++ b/repos/base-hw/src/core/include/spec/cortex_a15/cpu.h @@ -0,0 +1,69 @@ +/* + * \brief CPU driver for core + * \author Martin stein + * \date 2011-11-03 + */ + +/* + * Copyright (C) 2011-2012 Genode Labs GmbH + * + * This file is part of the Genode OS framework, which is distributed + * under the terms of the GNU General Public License version 2. + */ + +#ifndef _CPU_H_ +#define _CPU_H_ + +/* core includes */ +#include + +namespace Genode +{ + /** + * Part of CPU state that is not switched on every mode transition + */ + class Cpu_lazy_state { }; + + /** + * CPU driver for core + */ + class Cpu; +} + +namespace Kernel +{ + using Genode::Cpu_lazy_state; + using Genode::Cpu; +} + +class Genode::Cpu : public Arm_v7 +{ + public: + + /** + * Return wether to retry an undefined user instruction after this call + */ + bool retry_undefined_instr(Cpu_lazy_state *) { return false; } + + /** + * Return kernel name of the executing processor + */ + static unsigned executing_id(); + + /** + * Return kernel name of the primary processor + */ + static unsigned primary_id(); + + /************* + ** Dummies ** + *************/ + + static void tlb_insertions() { } + static void translation_added(addr_t, size_t) { } + static void prepare_proceeding(Cpu_lazy_state *, Cpu_lazy_state *) { } +}; + +void Genode::Arm_v7::finish_init_phys_kernel() { } + +#endif /* _CPU_H_ */ diff --git a/repos/base-hw/src/core/include/spec/cortex_a15/processor_driver_support.h b/repos/base-hw/src/core/include/spec/cortex_a15/processor_driver_support.h deleted file mode 100644 index 1bdce7ae2..000000000 --- a/repos/base-hw/src/core/include/spec/cortex_a15/processor_driver_support.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * \brief Processor driver for core - * \author Martin stein - * \date 2011-11-03 - */ - -/* - * Copyright (C) 2011-2012 Genode Labs GmbH - * - * This file is part of the Genode OS framework, which is distributed - * under the terms of the GNU General Public License version 2. - */ - -#ifndef _SPEC__CORTEX_A15__PROCESSOR_DRIVER_SUPPORT_H_ -#define _SPEC__CORTEX_A15__PROCESSOR_DRIVER_SUPPORT_H_ - -/* core includes */ -#include - -namespace Genode -{ - /** - * Part of processor state that is not switched on every mode transition - */ - class Processor_lazy_state { }; - - /** - * Processor driver for core - */ - class Cortex_a15; -} - -class Genode::Cortex_a15 : public Arm_v7 -{ - public: - - /** - * Return wether to retry an undefined user instruction after this call - */ - bool retry_undefined_instr(Processor_lazy_state *) { return false; } - - /************* - ** Dummies ** - *************/ - - static void tlb_insertions() { } - static void translation_added(addr_t, size_t) { } - static void prepare_proceeding(Processor_lazy_state *, - Processor_lazy_state *) { } -}; - - -void Genode::Arm_v7::finish_init_phys_kernel() { } - - -#endif /* _SPEC__CORTEX_A15__PROCESSOR_DRIVER_SUPPORT_H_ */ diff --git a/repos/base-hw/src/core/include/spec/cortex_a8/processor_driver.h b/repos/base-hw/src/core/include/spec/cortex_a8/cpu.h similarity index 65% rename from repos/base-hw/src/core/include/spec/cortex_a8/processor_driver.h rename to repos/base-hw/src/core/include/spec/cortex_a8/cpu.h index 71d3721fe..e94acb2e9 100644 --- a/repos/base-hw/src/core/include/spec/cortex_a8/processor_driver.h +++ b/repos/base-hw/src/core/include/spec/cortex_a8/cpu.h @@ -1,5 +1,5 @@ /* - * \brief Processor driver for core + * \brief CPU driver for core * \author Martin stein * \date 2011-11-03 */ @@ -11,26 +11,32 @@ * under the terms of the GNU General Public License version 2. */ -#ifndef _PROCESSOR_DRIVER_H_ -#define _PROCESSOR_DRIVER_H_ +#ifndef _CPU_H_ +#define _CPU_H_ /* core includes */ -#include +#include namespace Genode { /** - * Part of processor state that is not switched on every mode transition + * Part of CPU state that is not switched on every mode transition */ - class Processor_lazy_state { }; + class Cpu_lazy_state { }; /** - * Processor driver for core + * CPU driver for core */ - class Processor_driver; + class Cpu; } -class Genode::Processor_driver : public Arm_v7 +namespace Kernel +{ + using Genode::Cpu_lazy_state; + using Genode::Cpu; +} + +class Genode::Cpu : public Arm_v7 { public: @@ -39,16 +45,10 @@ class Genode::Processor_driver : public Arm_v7 */ static void tlb_insertions() { flush_tlb(); } - /** - * Prepare for the proceeding of a user - */ - static void prepare_proceeding(Processor_lazy_state *, - Processor_lazy_state *) { } - /** * Return wether to retry an undefined user instruction after this call */ - bool retry_undefined_instr(Processor_lazy_state *) { return false; } + bool retry_undefined_instr(Cpu_lazy_state *) { return false; } /** * Post processing after a translation was added to a translation table @@ -68,19 +68,23 @@ class Genode::Processor_driver : public Arm_v7 if (is_user()) Kernel::update_data_region(addr, size); } - /** - * Return kernel name of the primary processor - */ - static unsigned primary_id() { return 0; } - /** * Return kernel name of the executing processor */ - static unsigned executing_id() { return primary_id(); } -}; + static unsigned executing_id(); + /** + * Return kernel name of the primary processor + */ + static unsigned primary_id(); + + /************* + ** Dummies ** + *************/ + + static void prepare_proceeding(Cpu_lazy_state *, Cpu_lazy_state *) { } +}; void Genode::Arm_v7::finish_init_phys_kernel() { } - -#endif /* _PROCESSOR_DRIVER_H_ */ +#endif /* _CPU_H_ */ diff --git a/repos/base-hw/src/core/include/spec/cortex_a9/processor_driver.h b/repos/base-hw/src/core/include/spec/cortex_a9/cpu.h similarity index 80% rename from repos/base-hw/src/core/include/spec/cortex_a9/processor_driver.h rename to repos/base-hw/src/core/include/spec/cortex_a9/cpu.h index 0b67551cb..8c2a8cb3f 100644 --- a/repos/base-hw/src/core/include/spec/cortex_a9/processor_driver.h +++ b/repos/base-hw/src/core/include/spec/cortex_a9/cpu.h @@ -1,5 +1,5 @@ /* - * \brief Processor driver for core + * \brief CPU driver for core * \author Martin stein * \date 2011-11-03 */ @@ -11,29 +11,35 @@ * under the terms of the GNU General Public License version 2. */ -#ifndef _PROCESSOR_DRIVER_H_ -#define _PROCESSOR_DRIVER_H_ +#ifndef _CPU_H_ +#define _CPU_H_ /* core includes */ -#include +#include #include namespace Genode { /** - * Part of processor state that is not switched on every mode transition + * Part of CPU state that is not switched on every mode transition */ - class Processor_lazy_state; + class Cpu_lazy_state; /** - * Processor driver for core + * CPU driver for core */ - class Processor_driver; + class Cpu; } -class Genode::Processor_lazy_state +namespace Kernel { - friend class Processor_driver; + using Genode::Cpu_lazy_state; + using Genode::Cpu; +} + +class Genode::Cpu_lazy_state +{ + friend class Cpu; private: @@ -50,12 +56,12 @@ class Genode::Processor_lazy_state /** * Constructor */ - inline Processor_lazy_state(); + inline Cpu_lazy_state(); }; -class Genode::Processor_driver : public Arm_v7 +class Genode::Cpu : public Arm_v7 { - friend class Processor_lazy_state; + friend class Cpu_lazy_state; private: @@ -146,7 +152,7 @@ class Genode::Processor_driver : public Arm_v7 } }; - Processor_lazy_state * _advanced_fp_simd_state; + Cpu_lazy_state * _advanced_fp_simd_state; /** * Enable or disable the advanced FP/SIMD extension @@ -165,8 +171,7 @@ class Genode::Processor_driver : public Arm_v7 * * \param state processor state to save FP/SIMD state into */ - static void - _save_advanced_fp_simd_state(Processor_lazy_state * const state) + static void _save_advanced_fp_simd_state(Cpu_lazy_state * const state) { /* save system registers */ state->fpexc = Fpexc::read(); @@ -188,8 +193,7 @@ class Genode::Processor_driver : public Arm_v7 * * \param state processor state to load FP/SIMD state out of */ - static void - _load_advanced_fp_simd_state(Processor_lazy_state * const state) + static void _load_advanced_fp_simd_state(Cpu_lazy_state * const state) { /* load system registers */ Fpexc::write(state->fpexc); @@ -238,12 +242,7 @@ class Genode::Processor_driver : public Arm_v7 /** * Constructor */ - Processor_driver() : _advanced_fp_simd_state(0) { } - - /** - * Ensure that TLB insertions get applied - */ - static void tlb_insertions() { } + Cpu() : _advanced_fp_simd_state(0) { } /** * Initialize advanced FP/SIMD extension @@ -263,8 +262,8 @@ class Genode::Processor_driver : public Arm_v7 * \param old_state processor state of the last user * \param new_state processor state of the next user */ - static void prepare_proceeding(Processor_lazy_state * const old_state, - Processor_lazy_state * const new_state) + static void prepare_proceeding(Cpu_lazy_state * const old_state, + Cpu_lazy_state * const new_state) { if (old_state == new_state) { return; } _toggle_advanced_fp_simd(false); @@ -275,7 +274,7 @@ class Genode::Processor_driver : public Arm_v7 * * \param state processor state of the user */ - bool retry_undefined_instr(Processor_lazy_state * const state) + bool retry_undefined_instr(Cpu_lazy_state * const state) { if (_advanced_fp_simd_enabled()) { return false; } _toggle_advanced_fp_simd(true); @@ -290,34 +289,26 @@ class Genode::Processor_driver : public Arm_v7 } /** - * After a page-fault resolution nothing needs to be done + * Return kernel name of the executing processor */ - static void translation_added(Genode::addr_t addr, - Genode::size_t size) { } + static unsigned executing_id(); /** * Return kernel name of the primary processor */ - static unsigned primary_id() { return 0; } + static unsigned primary_id(); - /** - * Return kernel name of the executing processor - */ - static unsigned executing_id() { return primary_id(); } + /************* + ** Dummies ** + *************/ + + static void translation_added(addr_t, size_t) { } + static void tlb_insertions() { } }; +void Genode::Arm_v7::finish_init_phys_kernel() { Cpu::init_advanced_fp_simd(); } -void Genode::Arm_v7::finish_init_phys_kernel() -{ - Processor_driver::init_advanced_fp_simd(); -} - - -Genode::Processor_lazy_state::Processor_lazy_state() -{ - fpexc = Processor_driver::Fpexc::En::bits(1); -} - +Genode::Cpu_lazy_state::Cpu_lazy_state() { fpexc = Cpu::Fpexc::En::bits(1); } /* * Annotation 1 @@ -339,4 +330,4 @@ Genode::Processor_lazy_state::Processor_lazy_state() * head branch as from 2014.04.17. */ -#endif /* _PROCESSOR_DRIVER_H_ */ +#endif /* _CPU_H_ */ diff --git a/repos/base-hw/src/core/include/spec/cortex_a9/pic.h b/repos/base-hw/src/core/include/spec/cortex_a9/pic.h index 8cab24392..126c24ab6 100644 --- a/repos/base-hw/src/core/include/spec/cortex_a9/pic.h +++ b/repos/base-hw/src/core/include/spec/cortex_a9/pic.h @@ -16,7 +16,7 @@ /* core includes */ #include -#include +#include namespace Genode { @@ -28,15 +28,13 @@ namespace Genode class Genode::Pic : public Arm_gic { - private: - public: /** * Constructor */ - Pic() : Arm_gic(Processor_driver::PL390_DISTRIBUTOR_MMIO_BASE, - Processor_driver::PL390_CPU_MMIO_BASE) { } + Pic() : Arm_gic(Cpu::PL390_DISTRIBUTOR_MMIO_BASE, + Cpu::PL390_CPU_MMIO_BASE) { } /** * Mark interrupt 'i' unsecure diff --git a/repos/base-hw/src/core/include/spec/cortex_a9/timer.h b/repos/base-hw/src/core/include/spec/cortex_a9/timer.h index 7401da175..1ad399824 100644 --- a/repos/base-hw/src/core/include/spec/cortex_a9/timer.h +++ b/repos/base-hw/src/core/include/spec/cortex_a9/timer.h @@ -18,7 +18,7 @@ #include /* core includes */ -#include +#include namespace Genode { @@ -27,7 +27,7 @@ namespace Genode */ class Timer : public Mmio { - enum { TICS_PER_MS = Processor_driver::PRIVATE_TIMER_CLK / 1000, }; + enum { TICS_PER_MS = Cpu::PRIVATE_TIMER_CLK / 1000, }; /** * Load value register @@ -58,7 +58,7 @@ namespace Genode /** * Constructor, clears the interrupt output */ - Timer() : Mmio(Processor_driver::PRIVATE_TIMER_MMIO_BASE) + Timer() : Mmio(Cpu::PRIVATE_TIMER_MMIO_BASE) { write(0); _clear_interrupt(); @@ -69,7 +69,7 @@ namespace Genode */ static unsigned interrupt_id(unsigned) { - return Processor_driver::PRIVATE_TIMER_IRQ; + return Cpu::PRIVATE_TIMER_IRQ; } /** diff --git a/repos/base-hw/src/core/include/spec/odroid_xu/processor_driver.h b/repos/base-hw/src/core/include/spec/odroid_xu/processor_driver.h deleted file mode 100644 index ccc2f5a20..000000000 --- a/repos/base-hw/src/core/include/spec/odroid_xu/processor_driver.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * \brief Processor driver for core - * \author Martin Stein - * \date 2012-04-23 - */ - -/* - * Copyright (C) 2012 Genode Labs GmbH - * - * This file is part of the Genode OS framework, which is distributed - * under the terms of the GNU General Public License version 2. - */ - -#ifndef _PROCESSOR_DRIVER_H_ -#define _PROCESSOR_DRIVER_H_ - -/* core includes */ -#include - -namespace Genode -{ - /** - * Processor driver for core - */ - class Processor_driver : public Cortex_a15 - { - public: - - /** - * Return kernel name of the primary processor - */ - static unsigned primary_id() { return 0; } - - /** - * Return kernel name of the executing processor - */ - static unsigned executing_id() { return primary_id(); } - }; -} - -#endif /* _PROCESSOR_DRIVER_H_ */ diff --git a/repos/base-hw/src/core/include/spec/vea9x4/trustzone/pic.h b/repos/base-hw/src/core/include/spec/vea9x4/trustzone/pic.h new file mode 100644 index 000000000..d529d57d6 --- /dev/null +++ b/repos/base-hw/src/core/include/spec/vea9x4/trustzone/pic.h @@ -0,0 +1,77 @@ +/* + * \brief Programmable interrupt controller for core + * \author Martin Stein + * \author Stefan Kalkowski + * \date 2012-04-23 + */ + +/* + * Copyright (C) 2012-2013 Genode Labs GmbH + * + * This file is part of the Genode OS framework, which is distributed + * under the terms of the GNU General Public License version 2. + */ + +#ifndef _PIC_H_ +#define _PIC_H_ + +/* core includes */ +#include +#include + +namespace Genode +{ + /** + * Programmable interrupt controller for core + */ + class Pic; +} + +class Genode::Pic : public Arm_gic +{ + public: + + /** + * Constructor + */ + Pic() : Arm_gic(Cpu::PL390_DISTRIBUTOR_MMIO_BASE, + Cpu::PL390_CPU_MMIO_BASE) + { + /* configure every shared peripheral interrupt */ + for (unsigned i=MIN_SPI; i <= _max_interrupt; i++) { + _distr.write(0, i); + _distr.write(0, i); + _distr.write(0xff, i); + } + + /* disable the priority filter */ + _cpui.write(0xff); + + /* signal secure IRQ via FIQ interface */ + Cpui::Ctlr::access_t ctlr = 0; + Cpui::Ctlr::Enable_grp0::set(ctlr, 1); + Cpui::Ctlr::Enable_grp1::set(ctlr, 1); + Cpui::Ctlr::Fiq_en::set(ctlr, 1); + _cpui.write(ctlr); + + /* use whole band of prios */ + _cpui.write(Cpui::Bpr::NO_PREEMPTION); + + /* enable device */ + _distr.write(Distr::Ctlr::Enable::bits(1)); + } + + /** + * Mark interrupt 'i' unsecure + */ + void unsecure(unsigned const i) { + _distr.write(1, i); } +}; + + +bool Genode::Arm_gic::_use_security_ext() { return 1; } + + +namespace Kernel { class Pic : public Genode::Pic { }; } + +#endif /* _PIC_H_ */ diff --git a/repos/base-hw/src/core/platform_thread.cc b/repos/base-hw/src/core/platform_thread.cc index 03ae1d5a7..c367d0499 100644 --- a/repos/base-hw/src/core/platform_thread.cc +++ b/repos/base-hw/src/core/platform_thread.cc @@ -98,7 +98,7 @@ Platform_thread::Platform_thread(const char * const label, sizeof(Native_utcb) / get_page_size()); /* set-up default start-info */ - _utcb_core_addr->core_start_info()->init(Processor_driver::primary_id()); + _utcb_core_addr->core_start_info()->init(Cpu::primary_id()); /* create kernel object */ _id = Kernel::new_thread(_kernel_thread, Kernel::Priority::MAX, _label); @@ -202,7 +202,7 @@ int Platform_thread::start(void * const ip, void * const sp) /* determine kernel name of targeted processor */ unsigned processor_id; if (_location.valid()) { processor_id = _location.xpos(); } - else { processor_id = Processor_driver::primary_id(); } + else { processor_id = Cpu::primary_id(); } /* start executing new thread */ _utcb_core_addr->start_info()->init(_id, _utcb); diff --git a/repos/base-hw/src/core/spec/arndale/cpu.cc b/repos/base-hw/src/core/spec/arndale/cpu.cc new file mode 100644 index 000000000..eceb77378 --- /dev/null +++ b/repos/base-hw/src/core/spec/arndale/cpu.cc @@ -0,0 +1,22 @@ +/* + * \brief CPU driver for core + * \author Martin stein + * \date 2011-11-03 + */ + +/* + * Copyright (C) 2011-2012 Genode Labs GmbH + * + * This file is part of the Genode OS framework, which is distributed + * under the terms of the GNU General Public License version 2. + */ + +/* core includes */ +#include +#include + +using namespace Genode; + +unsigned Cpu::executing_id() { return Mpidr::Aff_0::get(Mpidr::read()); } + +unsigned Cpu::primary_id() { return Board::PRIMARY_MPIDR_AFF_0; } diff --git a/repos/base-hw/src/core/spec/arndale/platform_support.cc b/repos/base-hw/src/core/spec/arndale/platform_support.cc index f197c2f39..e89dee80f 100644 --- a/repos/base-hw/src/core/spec/arndale/platform_support.cc +++ b/repos/base-hw/src/core/spec/arndale/platform_support.cc @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include using namespace Genode; @@ -53,4 +53,4 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i) } -Processor_driver::User_context::User_context() { cpsr = Psr::init_user(); } +Cpu::User_context::User_context() { cpsr = Psr::init_user(); } \ No newline at end of file diff --git a/repos/base-hw/src/core/spec/imx31/platform_support.cc b/repos/base-hw/src/core/spec/imx31/platform_support.cc index 2f2622290..5999bcdfe 100644 --- a/repos/base-hw/src/core/spec/imx31/platform_support.cc +++ b/repos/base-hw/src/core/spec/imx31/platform_support.cc @@ -15,7 +15,7 @@ #include #include #include -#include +#include using namespace Genode; @@ -69,4 +69,4 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i) } -Processor_driver::User_context::User_context() { cpsr = Psr::init_user(); } +Cpu::User_context::User_context() { cpsr = Psr::init_user(); } diff --git a/repos/base-hw/src/core/spec/imx53/platform_support.cc b/repos/base-hw/src/core/spec/imx53/platform_support.cc index dfae34b92..e88374bf3 100644 --- a/repos/base-hw/src/core/spec/imx53/platform_support.cc +++ b/repos/base-hw/src/core/spec/imx53/platform_support.cc @@ -15,7 +15,7 @@ #include #include #include -#include +#include using namespace Genode; @@ -59,4 +59,4 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i) } -Processor_driver::User_context::User_context() { cpsr = Psr::init_user(); } +Cpu::User_context::User_context() { cpsr = Psr::init_user(); } diff --git a/repos/base-hw/src/core/spec/imx53/trustzone/platform_support.cc b/repos/base-hw/src/core/spec/imx53/trustzone/platform_support.cc index 77cf795f4..fc1437884 100644 --- a/repos/base-hw/src/core/spec/imx53/trustzone/platform_support.cc +++ b/repos/base-hw/src/core/spec/imx53/trustzone/platform_support.cc @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include @@ -37,10 +37,10 @@ void Kernel::init_trustzone(Pic * pic) return; } /* set exception vector entry */ - Processor_driver::mon_exception_entry_at((Genode::addr_t)&_mon_kernel_entry); + Cpu::mon_exception_entry_at((Genode::addr_t)&_mon_kernel_entry); /* enable coprocessor access for TZ VMs */ - Processor_driver::allow_coprocessor_nonsecure(); + Cpu::allow_coprocessor_nonsecure(); /* configure non-secure interrupts */ for (unsigned i = 0; i < Pic::NR_OF_IRQ; i++) { @@ -101,4 +101,4 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i) } -Processor_driver::User_context::User_context() { cpsr = Psr::init_user_with_trustzone(); } +Cpu::User_context::User_context() { cpsr = Psr::init_user_with_trustzone(); } diff --git a/repos/base-hw/src/core/spec/odroid_xu/platform_support.cc b/repos/base-hw/src/core/spec/odroid_xu/platform_support.cc index 5f7ede089..54e793469 100644 --- a/repos/base-hw/src/core/spec/odroid_xu/platform_support.cc +++ b/repos/base-hw/src/core/spec/odroid_xu/platform_support.cc @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include using namespace Genode; @@ -51,4 +51,4 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i) } -Processor_driver::User_context::User_context() { cpsr = Psr::init_user(); } +Cpu::User_context::User_context() { cpsr = Psr::init_user(); } diff --git a/repos/base-hw/src/core/spec/panda/platform_support.cc b/repos/base-hw/src/core/spec/panda/platform_support.cc index e57d78baf..65c51ab49 100644 --- a/repos/base-hw/src/core/spec/panda/platform_support.cc +++ b/repos/base-hw/src/core/spec/panda/platform_support.cc @@ -14,7 +14,7 @@ /* core includes */ #include #include -#include +#include #include #include @@ -62,7 +62,7 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i) } -Processor_driver::User_context::User_context() { cpsr = Psr::init_user(); } +Cpu::User_context::User_context() { cpsr = Psr::init_user(); } static Board::Pl310 * l2_cache() { diff --git a/repos/base-hw/src/core/spec/pbxa9/platform_support.cc b/repos/base-hw/src/core/spec/pbxa9/platform_support.cc index 3cc331396..19969c55b 100644 --- a/repos/base-hw/src/core/spec/pbxa9/platform_support.cc +++ b/repos/base-hw/src/core/spec/pbxa9/platform_support.cc @@ -14,7 +14,7 @@ /* core includes */ #include #include -#include +#include #include using namespace Genode; @@ -56,4 +56,4 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i) } -Processor_driver::User_context::User_context() { cpsr = Psr::init_user(); } +Cpu::User_context::User_context() { cpsr = Psr::init_user(); } diff --git a/repos/base-hw/src/core/spec/rpi/platform_support.cc b/repos/base-hw/src/core/spec/rpi/platform_support.cc index 247dfc047..de83f4d67 100644 --- a/repos/base-hw/src/core/spec/rpi/platform_support.cc +++ b/repos/base-hw/src/core/spec/rpi/platform_support.cc @@ -14,7 +14,7 @@ /* core includes */ #include #include -#include +#include using namespace Genode; @@ -56,4 +56,4 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i) } -Processor_driver::User_context::User_context() { cpsr = Psr::init_user(); } +Cpu::User_context::User_context() { cpsr = Psr::init_user(); } diff --git a/repos/base-hw/src/core/spec/vea9x4/platform_support.cc b/repos/base-hw/src/core/spec/vea9x4/platform_support.cc index 84fd95664..4c341acf1 100644 --- a/repos/base-hw/src/core/spec/vea9x4/platform_support.cc +++ b/repos/base-hw/src/core/spec/vea9x4/platform_support.cc @@ -14,7 +14,7 @@ /* core includes */ #include #include -#include +#include #include using namespace Genode; @@ -59,4 +59,4 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i) } -Processor_driver::User_context::User_context() { cpsr = Psr::init_user(); } +Cpu::User_context::User_context() { cpsr = Psr::init_user(); } diff --git a/repos/base-hw/src/core/spec/vea9x4/trustzone/pic.cc b/repos/base-hw/src/core/spec/vea9x4/trustzone/pic.cc index 0487d07fd..0e7af5103 100644 --- a/repos/base-hw/src/core/spec/vea9x4/trustzone/pic.cc +++ b/repos/base-hw/src/core/spec/vea9x4/trustzone/pic.cc @@ -22,20 +22,19 @@ void Arm_gic::_init() for (unsigned i=MIN_SPI; i <= _max_interrupt; i++) { _distr.write(0, i); _distr.write(0, i); - _distr.write( - Distr::Itargetsr::ALL, i); + _distr.write(0xff, i); } /* disable the priority filter */ - _cpu.write(0xff); + _cpui.write(0xff); /* signal secure IRQ via FIQ interface */ - _cpu.write(Cpu::Ctlr::Enable_grp0::bits(1) | - Cpu::Ctlr::Enable_grp1::bits(1) | - Cpu::Ctlr::Fiq_en::bits(1)); + _cpui.write(Cpui::Ctlr::Enable_grp0::bits(1) | + Cpui::Ctlr::Enable_grp1::bits(1) | + Cpui::Ctlr::Fiq_en::bits(1)); /* use whole band of prios */ - _cpu.write(Cpu::Bpr::NO_PREEMPTION); + _cpui.write(Cpui::Bpr::NO_PREEMPTION); /* enable device */ _distr.write(Distr::Ctlr::Enable::bits(1)); diff --git a/repos/base-hw/src/core/spec/vea9x4/trustzone/platform_support.cc b/repos/base-hw/src/core/spec/vea9x4/trustzone/platform_support.cc index 6966deba6..0ddc113fe 100644 --- a/repos/base-hw/src/core/spec/vea9x4/trustzone/platform_support.cc +++ b/repos/base-hw/src/core/spec/vea9x4/trustzone/platform_support.cc @@ -15,7 +15,7 @@ /* core includes */ #include -#include +#include #include #include #include @@ -35,10 +35,10 @@ void Kernel::init_trustzone(Pic * pic) return; } /* set exception vector entry */ - Processor_driver::mon_exception_entry_at((Genode::addr_t)&_mon_kernel_entry); + Cpu::mon_exception_entry_at((Genode::addr_t)&_mon_kernel_entry); /* enable coprocessor access for TZ VMs */ - Processor_driver::allow_coprocessor_nonsecure(); + Cpu::allow_coprocessor_nonsecure(); /* set unsecure IRQs */ pic->unsecure(34); //Timer 0/1 @@ -92,4 +92,4 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i) } -Processor_driver::User_context::User_context() { cpsr = Psr::init_user_with_trustzone(); } +Cpu::User_context::User_context() { cpsr = Psr::init_user_with_trustzone(); }