hw: enable SMP for Wandboard (fix #2253)
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@ -14,7 +14,7 @@ INC_DIR += $(REP_DIR)/src/core/include/spec/imx
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SRC_CC += platform_services.cc
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SRC_CC += platform_services.cc
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SRC_CC += spec/imx6/platform_support.cc
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SRC_CC += spec/imx6/platform_support.cc
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NR_OF_CPUS = 1
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NR_OF_CPUS = 4
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# include less specific configuration
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# include less specific configuration
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include $(REP_DIR)/lib/mk/spec/cortex_a9/core-hw.inc
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include $(REP_DIR)/lib/mk/spec/cortex_a9/core-hw.inc
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@ -19,21 +19,56 @@
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#include <spec/imx/board_support.h>
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#include <spec/imx/board_support.h>
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#include <spec/cortex_a9/board_support.h>
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#include <spec/cortex_a9/board_support.h>
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namespace Genode
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namespace Genode { class Board; }
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{
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/**
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* Board driver
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*/
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class Board : public Imx::Board, public Cortex_a9::Board
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{
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public:
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void init()
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class Genode::Board : public Imx::Board, public Cortex_a9::Board
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{
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private:
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struct Src : Mmio
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{
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Src() : Mmio(SRC_MMIO_BASE) {}
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struct Scr : Register<0x0, 32>
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{
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{
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Imx::Board::init();
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struct Core_1_reset : Bitfield<14,1> {};
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Cortex_a9::Board::init();
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struct Core_2_reset : Bitfield<15,1> {};
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struct Core_3_reset : Bitfield<16,1> {};
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struct Core_1_enable : Bitfield<22,1> {};
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struct Core_2_enable : Bitfield<23,1> {};
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struct Core_3_enable : Bitfield<24,1> {};
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};
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struct Gpr1 : Register<0x20, 32> {}; /* ep core 0 */
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struct Gpr3 : Register<0x28, 32> {}; /* ep core 1 */
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struct Gpr5 : Register<0x30, 32> {}; /* ep core 2 */
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struct Gpr7 : Register<0x38, 32> {}; /* ep core 3 */
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void entrypoint(void * entry)
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{
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write<Gpr3>((Gpr3::access_t)entry);
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write<Gpr5>((Gpr5::access_t)entry);
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write<Gpr7>((Gpr7::access_t)entry);
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Scr::access_t v = read<Scr>();
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Scr::Core_1_enable::set(v,1);
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Scr::Core_1_reset::set(v,1);
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Scr::Core_2_enable::set(v,1);
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Scr::Core_3_reset::set(v,1);
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Scr::Core_3_enable::set(v,1);
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Scr::Core_3_reset::set(v,1);
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write<Scr>(v);
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}
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}
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};
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} _src;
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}
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public:
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void init()
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{
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Imx::Board::init();
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Cortex_a9::Board::init();
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}
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void wake_up_all_cpus(void *entry) { _src.entrypoint(entry); }
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};
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#endif /* _CORE__INCLUDE__SPEC__IMX6__BOARD_H_ */
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#endif /* _CORE__INCLUDE__SPEC__IMX6__BOARD_H_ */
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@ -111,6 +111,12 @@ void Kernel::Cpu::init(Kernel::Pic &pic, Kernel::Pd & core_pd, Genode::Board & b
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Actlr::enable_smp();
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Actlr::enable_smp();
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smp_coherency_enabled.inc();
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smp_coherency_enabled.inc();
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/*
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* strangely, some older versions (imx6) seem to not work cache coherent
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* until SMP bit is set, so write back the variable here.
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*/
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clean_invalidate_inner_data_cache();
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/* wait for other cores' coherency activation */
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/* wait for other cores' coherency activation */
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smp_coherency_enabled.wait_for(NR_OF_CPUS);
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smp_coherency_enabled.wait_for(NR_OF_CPUS);
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@ -66,6 +66,9 @@ struct Genode::Board_base
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PL310_MMIO_BASE = 0x00a02000,
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PL310_MMIO_BASE = 0x00a02000,
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PL310_MMIO_SIZE = 0x00001000,
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PL310_MMIO_SIZE = 0x00001000,
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/* System reset controller */
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SRC_MMIO_BASE = 0x20d8000,
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/* CPU cache */
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/* CPU cache */
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CACHE_LINE_SIZE_LOG2 = 5,
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CACHE_LINE_SIZE_LOG2 = 5,
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