Martin Stein
Christian Helmuth
parent
6ec39d8df5
commit
c6417051ce
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@ -22,19 +22,112 @@
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namespace Genode
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{
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/*
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* Redirection table entry
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*/
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struct Irte;
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/**
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* IO advanced programmable interrupt controller
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*/
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class Ioapic;
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/**
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* Programmable interrupt controller for core
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*/
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class Pic;
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}
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struct Genode::Irte : Register<64>
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{
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struct Pol : Bitfield<13, 1> { };
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struct Trg : Bitfield<15, 1> { };
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struct Mask : Bitfield<16, 1> { };
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};
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class Genode::Pic : public Mmio
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class Genode::Ioapic : public Mmio
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{
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private:
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enum { REMAP_BASE = Board::VECTOR_REMAP_BASE };
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uint8_t _irt_count;
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enum {
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/* Number of Redirection Table entries */
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IRTE_COUNT = 0x17,
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/* Register selectors */
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IOAPICVER = 0x01,
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IOREDTBL = 0x10,
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};
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/**
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* Create redirection table entry for given IRQ
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*/
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Irte::access_t _create_irt_entry(unsigned const irq)
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{
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Irte::access_t irte = REMAP_BASE + irq;
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/* Use level-triggered, low-active mode for non-legacy IRQs */
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if (irq > Board::ISA_IRQ_END) {
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Irte::Pol::set(irte, 1);
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Irte::Trg::set(irte, 1);
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}
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return irte;
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}
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/**
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* Return whether 'irq' is an edge-triggered interrupt
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*/
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bool _edge_triggered(unsigned const irq)
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{
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return irq <= REMAP_BASE + Board::ISA_IRQ_END ||
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irq > REMAP_BASE + IRTE_COUNT;
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}
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public:
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Ioapic() : Mmio(Board::MMIO_IOAPIC_BASE)
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{
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/* Remap all supported IRQs */
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for (unsigned i = 0; i <= IRTE_COUNT; i++) {
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Irte::access_t irte = _create_irt_entry(i);
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write<Ioregsel>(IOREDTBL + 2 * i + 1);
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write<Iowin>(irte >> Iowin::ACCESS_WIDTH);
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write<Ioregsel>(IOREDTBL + 2 * i);
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write<Iowin>(irte);
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}
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};
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/* Set/unset mask bit of IRTE for given vector */
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void toggle_mask(unsigned const vector, bool const set)
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{
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/*
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* Only mask existing RTEs and do *not* mask edge-triggered
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* interrupts to avoid losing them while masked, see Intel
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* 82093AA I/O Advanced Programmable Interrupt Controller
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* (IOAPIC) specification, section 3.4.2, "Interrupt Mask"
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* flag and edge-triggered interrupts or:
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* http://yarchive.net/comp/linux/edge_triggered_interrupts.html
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*/
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if (_edge_triggered(vector)) { return; }
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write<Ioregsel>(IOREDTBL + (2 * (vector - REMAP_BASE)));
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Irte::access_t irte = read<Iowin>();
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Irte::Mask::set(irte, set);
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write<Iowin>(irte);
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}
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/* Registers */
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struct Ioregsel : Register<0x00, 32> { };
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struct Iowin : Register<0x10, 32> { };
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};
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class Genode::Pic : public Mmio
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{
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private:
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/* Registers */
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struct EOI : Register<0x0b0, 32, true> { };
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struct Svr : Register<0x0f0, 32>
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@ -48,92 +141,6 @@ class Genode::Pic : public Mmio
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*/
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struct Isr : Register_array<0x100, 32, 8 * 4, 32> { };
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class Ioapic : public Mmio
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{
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private:
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uint8_t _irt_count;
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enum {
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/* Number of Redirection Table entries */
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IRTE_COUNT = 0x17,
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IRTE_BIT_POL = 13,
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IRTE_BIT_TRG = 15,
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IRTE_BIT_MASK = 16,
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/* Register selectors */
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IOAPICVER = 0x01,
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IOREDTBL = 0x10,
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};
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/**
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* Create redirection table entry for given IRQ
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*/
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uint64_t _create_irt_entry(unsigned irq)
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{
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uint32_t entry = REMAP_BASE + irq;
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if (irq > Board::ISA_IRQ_END) {
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/* Use level-triggered, high-active mode for non-legacy
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* IRQs */
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entry |= 1 << IRTE_BIT_POL | 1 << IRTE_BIT_TRG;
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}
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return entry;
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}
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/**
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* Return whether 'irq' is an edge-triggered interrupt
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*/
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bool _edge_triggered(unsigned const irq)
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{
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return irq <= REMAP_BASE + Board::ISA_IRQ_END ||
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irq > REMAP_BASE + IRTE_COUNT;
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}
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public:
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Ioapic() : Mmio(Board::MMIO_IOAPIC_BASE)
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{
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/* Remap all supported IRQs */
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for (unsigned i = 0; i <= IRTE_COUNT; i++) {
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uint64_t val = _create_irt_entry(i);
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write<Ioregsel>(IOREDTBL + 2 * i + 1);
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write<Iowin>(val >> 32);
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write<Ioregsel>(IOREDTBL + 2 * i);
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write<Iowin>(val & 0xffffffff);
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}
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};
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/* Set/unset mask bit of IRTE for given vector */
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void toggle_mask(unsigned const vector, bool const set)
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{
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/*
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* Only mask existing RTEs and do *not* mask edge-triggered
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* interrupts to avoid losing them while masked, see Intel
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* 82093AA I/O Advanced Programmable Interrupt Controller
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* (IOAPIC) specification, section 3.4.2, "Interrupt Mask"
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* flag and edge-triggered interrupts or:
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* http://yarchive.net/comp/linux/edge_triggered_interrupts.html
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*/
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if (_edge_triggered(vector)) { return; }
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write<Ioregsel>(IOREDTBL + (2 * (vector - REMAP_BASE)));
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uint32_t val = read<Iowin>();
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if (set) {
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val |= 1 << IRTE_BIT_MASK;
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} else {
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val &= ~(1 << IRTE_BIT_MASK);
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}
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write<Iowin>(val);
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}
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/* Registers */
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struct Ioregsel : Register<0x00, 32> { };
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struct Iowin : Register<0x10, 32> { };
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};
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Ioapic _ioapic;
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/**
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