Johannes Schlatow
Norman Feske
parent
abd536d5d3
commit
bfe0031304
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@ -5,8 +5,10 @@ SRC_S += bootstrap/spec/arm/crt0.s
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SRC_CC += bootstrap/spec/arm/cpu.cc
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SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
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SRC_CC += bootstrap/spec/arm/pic.cc
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SRC_CC += bootstrap/spec/zynq_qemu/platform.cc
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SRC_CC += bootstrap/spec/zynq/platform.cc
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SRC_CC += hw/spec/arm/arm_v7_cpu.cc
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SRC_CC += hw/spec/32bit/memory_map.cc
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NR_OF_CPUS = 1
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include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
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@ -28,6 +28,13 @@ struct Bootstrap::Actlr : Bootstrap::Cpu::Actlr
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Smp::set(v, 1);
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write(v);
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}
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static void disable_smp()
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{
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auto v = read();
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Smp::set(v, 0);
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write(v);
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}
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};
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#endif /* _SRC__BOOTSTRAP__SPEC__ARM__CORTEX_A9_ACTLR_H_ */
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@ -109,6 +109,7 @@ unsigned Bootstrap::Platform::enable_mmu()
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Cpu::Sctlr::init();
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Cpu::Cpsr::init();
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Actlr::disable_smp();
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/* locally initialize interrupt controller */
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pic.init_cpu_local();
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@ -28,7 +28,7 @@ void Bootstrap::Cpu::enable_mmu_and_caches(Genode::addr_t table)
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Ttbr::access_t ttbr = Ttbr::Ba::masked(table);
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Ttbr::Rgn::set(ttbr, Ttbr::CACHEABLE);
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if (Mpidr::read()) { /* check for SMP system */
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if (Mpidr::Me::get(Mpidr::read())) { /* check for SMP system */
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Ttbr::Irgn::set(ttbr, Ttbr::CACHEABLE);
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Ttbr::S::set(ttbr, 1);
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} else
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@ -44,6 +44,8 @@ struct Bootstrap::Actlr
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{
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static void enable_smp() {
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Hw::call_panda_firmware(Hw::CPU_ACTLR_SMP_BIT_RAISE, 0); }
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static void disable_smp() { /* not implemented */ }
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};
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@ -23,7 +23,7 @@ Bootstrap::Platform::Board::Board()
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late_ram_regions(Memory_region { RAM_0_BASE, 0x1000 }),
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core_mmio(Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
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CORTEX_A9_PRIVATE_MEM_SIZE },
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Memory_region { UART_0_MMIO_BASE,
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Memory_region { UART_BASE,
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UART_SIZE },
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Memory_region { PL310_MMIO_BASE,
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PL310_MMIO_SIZE }) { }
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@ -31,3 +31,19 @@ Bootstrap::Platform::Board::Board()
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bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata) {
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return false; }
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void Bootstrap::Cpu::wake_up_all_cpus(void* ip) {
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struct Wakeup_generator : Genode::Mmio
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{
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struct Core1_boot_addr : Register<0x0, 32> { };
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Wakeup_generator(void * const ip) : Mmio(CORE1_ENTRY)
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{
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write<Core1_boot_addr>((addr_t)ip);
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}
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};
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Wakeup_generator wgen(ip);
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asm volatile("dsb\n"
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"sev\n");
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}
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@ -42,8 +42,6 @@ struct Genode::Arm_cpu : public Hw::Arm_cpu
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*/
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struct Ttbr0 : Hw::Arm_cpu::Ttbr0
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{
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enum Memory_region { NON_CACHEABLE = 0, CACHEABLE = 1 };
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/**
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* Return initialized value
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*
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@ -52,9 +50,9 @@ struct Genode::Arm_cpu : public Hw::Arm_cpu
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static access_t init(addr_t const table)
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{
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access_t v = Ttbr::Ba::masked((addr_t)table);
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Ttbr::Rgn::set(v, CACHEABLE);
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Ttbr::Rgn::set(v, Ttbr::CACHEABLE);
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Ttbr::S::set(v, Board::SMP ? 1 : 0);
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if (Board::SMP) Ttbr::Irgn::set(v, CACHEABLE);
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if (Board::SMP) Ttbr::Irgn::set(v, Ttbr::CACHEABLE);
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else Ttbr::C::set(v, 1);
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return v;
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}
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@ -32,7 +32,8 @@ struct Hw::Arm_cpu
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/* Multiprocessor Affinity Register */
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ARM_CP15_REGISTER_32BIT(Mpidr, c0, c0, 0, 5,
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struct Aff_0 : Bitfield<0, 8> { }; /* affinity value 0 */
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struct Aff_0 : Bitfield<0, 8> { }; /* affinity value 0 */
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struct Me : Bitfield<31, 1> { }; /* multiprocessing extension */
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);
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/* System Control Register */
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@ -90,7 +91,7 @@ struct Hw::Arm_cpu
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*/
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struct Ttbr : Genode::Register<32>
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{
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enum Memory_region { NON_CACHEABLE = 0, CACHEABLE = 1 };
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enum Memory_region { CACHEABLE = 1 };
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struct C : Bitfield<0,1> { }; /* inner cacheable */
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struct S : Bitfield<1,1> { }; /* shareable */
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@ -47,6 +47,9 @@ namespace Zynq {
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CORTEX_A9_PRIVATE_MEM_BASE = 0xf8f00000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
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/* entrypoint address of secondary cpu */
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CORE1_ENTRY = 0xfffffff0,
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/* CPU cache */
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PL310_MMIO_BASE = MMIO_1_BASE + 0xF02000,
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PL310_MMIO_SIZE = 0x1000,
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@ -8,6 +8,7 @@ if {
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![have_spec arndale] &&
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![have_spec wand_quad] &&
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![have_spec panda] &&
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![expr [have_spec zynq] && ![have_spec zynq_qemu] ] &&
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![expr [have_spec x86_32] && [have_spec foc] ] &&
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![expr [have_spec x86_64] && [have_spec foc] ] &&
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![have_spec nova] &&
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