diff --git a/repos/base-hw/src/core/imx53/pic_base.h b/repos/base-hw/src/core/imx53/pic_base.h
index 36e1b59d4..8993967cc 100644
--- a/repos/base-hw/src/core/imx53/pic_base.h
+++ b/repos/base-hw/src/core/imx53/pic_base.h
@@ -31,7 +31,7 @@ namespace Imx53
 	{
 		public:
 
-			enum { MAX_INTERRUPT_ID = 108 };
+			enum { NR_OF_IRQ = 109 };
 
 		protected:
 
@@ -63,7 +63,7 @@ namespace Imx53
 			/**
 			 * Interrupt security registers
 			 */
-			struct Intsec : Register_array<0x80, 32, MAX_INTERRUPT_ID, 1>
+			struct Intsec : Register_array<0x80, 32, NR_OF_IRQ, 1>
 			{
 				struct Nonsecure : Bitfield<0, 1> { };
 			};
@@ -71,7 +71,7 @@ namespace Imx53
 			/**
 			 * Interrupt set enable registers
 			 */
-			struct Enset : Register_array<0x100, 32, MAX_INTERRUPT_ID, 1, true>
+			struct Enset : Register_array<0x100, 32, NR_OF_IRQ, 1, true>
 			{
 				struct Set_enable : Bitfield<0, 1> { };
 			};
@@ -79,7 +79,7 @@ namespace Imx53
 			/**
 			 * Interrupt clear enable registers
 			 */
-			struct Enclear : Register_array<0x180, 32, MAX_INTERRUPT_ID, 1, true>
+			struct Enclear : Register_array<0x180, 32, NR_OF_IRQ, 1, true>
 			{
 				struct Clear_enable : Bitfield<0, 1> { };
 			};
@@ -87,7 +87,7 @@ namespace Imx53
 			/**
 			 * Interrupt priority level registers
 			 */
-			struct Priority  : Register_array<0x400, 32, MAX_INTERRUPT_ID, 8>
+			struct Priority  : Register_array<0x400, 32, NR_OF_IRQ, 8>
 			{
 				enum { MIN_PRIO = 0xff };
 			};
@@ -95,7 +95,7 @@ namespace Imx53
 			/**
 			 * Pending registers
 			 */
-			struct Pndr  : Register_array<0xd00, 32, MAX_INTERRUPT_ID, 1>
+			struct Pndr  : Register_array<0xd00, 32, NR_OF_IRQ, 1>
 			{
 				struct Pending : Bitfield<0, 1> { };
 			};
@@ -103,7 +103,7 @@ namespace Imx53
 			/**
 			 * Highest interrupt pending registers
 			 */
-			struct Hipndr  : Register_array<0xd80, 32, MAX_INTERRUPT_ID, 1, true>
+			struct Hipndr  : Register_array<0xd80, 32, NR_OF_IRQ, 1, true>
 			{
 				struct Pending : Bitfield<0, 1> { };
 			};
@@ -120,7 +120,7 @@ namespace Imx53
 			 */
 			Pic_base() : Mmio(Board::TZIC_MMIO_BASE)
 			{
-				for (unsigned i = 0; i <= MAX_INTERRUPT_ID; i++) {
+				for (unsigned i = 0; i < NR_OF_IRQ; i++) {
 					write<Intsec::Nonsecure>(1, i);
 					write<Enclear::Clear_enable>(1, i);
 				}
@@ -142,7 +142,7 @@ namespace Imx53
 			 */
 			bool take_request(unsigned & i)
 			{
-				for (unsigned j = 0; j <= MAX_INTERRUPT_ID; j++) {
+				for (unsigned j = 0; j < NR_OF_IRQ; j++) {
 					if (read<Hipndr::Pending>(j)) {
 						i = j;
 						return true;
@@ -160,14 +160,14 @@ namespace Imx53
 			 * Validate request number 'i'
 			 */
 			bool valid(unsigned const i) const {
-				return i <= MAX_INTERRUPT_ID; }
+				return i < NR_OF_IRQ; }
 
 			/**
 			 * Unmask all interrupts
 			 */
 			void unmask()
 			{
-				for (unsigned i=0; i <= MAX_INTERRUPT_ID; i++)
+				for (unsigned i=0; i < NR_OF_IRQ; i++)
 					write<Enset::Set_enable>(1, i);
 			}
 
@@ -176,7 +176,7 @@ namespace Imx53
 			 */
 			void mask()
 			{
-				for (unsigned i=0; i <= MAX_INTERRUPT_ID; i++)
+				for (unsigned i=0; i < NR_OF_IRQ; i++)
 					write<Enclear::Clear_enable>(1, i);
 			}
 
@@ -187,7 +187,7 @@ namespace Imx53
 			 */
 			void unmask(unsigned const interrupt_id, unsigned)
 			{
-				if (interrupt_id <= MAX_INTERRUPT_ID) {
+				if (interrupt_id < NR_OF_IRQ) {
 					write<Enset::Set_enable>(1, interrupt_id);
 				}
 			}
@@ -197,7 +197,7 @@ namespace Imx53
 			 */
 			void mask(unsigned const i)
 			{
-				if (i <= MAX_INTERRUPT_ID)
+				if (i < NR_OF_IRQ)
 					write<Enclear::Clear_enable>(1, i);
 			}
 
diff --git a/repos/base-hw/src/core/imx53/trustzone/pic.h b/repos/base-hw/src/core/imx53/trustzone/pic.h
index 6641c8198..0caec3f38 100644
--- a/repos/base-hw/src/core/imx53/trustzone/pic.h
+++ b/repos/base-hw/src/core/imx53/trustzone/pic.h
@@ -33,7 +33,7 @@ namespace Imx53
 
 			Pic()
 			{
-				for (unsigned i = 0; i <= MAX_INTERRUPT_ID; i++) {
+				for (unsigned i = 0; i < NR_OF_IRQ; i++) {
 					write<Intsec::Nonsecure>(0, i);
 					write<Priority>(0, i);
 				}
@@ -43,7 +43,7 @@ namespace Imx53
 
 			void unsecure(unsigned const i)
 			{
-				if (i <= MAX_INTERRUPT_ID) {
+				if (i < NR_OF_IRQ) {
 					write<Intsec::Nonsecure>(1, i);
 					write<Priority>(0x80, i);
 				}
@@ -51,7 +51,7 @@ namespace Imx53
 
 			void secure(unsigned const i)
 			{
-				if (i <= MAX_INTERRUPT_ID) {
+				if (i < NR_OF_IRQ) {
 					write<Intsec::Nonsecure>(0, i);
 					write<Priority>(0, i);
 				}
diff --git a/repos/base-hw/src/core/imx53/trustzone/trustzone.cc b/repos/base-hw/src/core/imx53/trustzone/trustzone.cc
index b98fd1e57..d9e720f05 100644
--- a/repos/base-hw/src/core/imx53/trustzone/trustzone.cc
+++ b/repos/base-hw/src/core/imx53/trustzone/trustzone.cc
@@ -38,7 +38,7 @@ void Kernel::init_trustzone(Pic * pic)
 	Processor_driver::allow_coprocessor_nonsecure();
 
 	/* configure non-secure interrupts */
-	for (unsigned i = 0; i <= Pic::MAX_INTERRUPT_ID; i++) {
+	for (unsigned i = 0; i < Pic::NR_OF_IRQ; i++) {
 		if ((i != Imx53::Board::EPIT_1_IRQ) &&
 			(i != Imx53::Board::EPIT_2_IRQ) &&
 			(i != Imx53::Board::I2C_2_IRQ)  &&
diff --git a/repos/base-hw/src/core/kernel/kernel.cc b/repos/base-hw/src/core/kernel/kernel.cc
index 8808489b1..588660e68 100644
--- a/repos/base-hw/src/core/kernel/kernel.cc
+++ b/repos/base-hw/src/core/kernel/kernel.cc
@@ -303,8 +303,8 @@ extern "C" void init_kernel_multiprocessor()
 		t.init(processor, core_pd(), &utcb, 1);
 
 		/* initialize interrupt objects */
-		static Genode::uint8_t _irqs[(Pic::MAX_INTERRUPT_ID+1) * sizeof(Irq)];
-		for (unsigned i = 0; i <= Pic::MAX_INTERRUPT_ID; i++) {
+		static Genode::uint8_t _irqs[Pic::NR_OF_IRQ * sizeof(Irq)];
+		for (unsigned i = 0; i < Pic::NR_OF_IRQ; i++) {
 			if (private_interrupt(i)) { continue; }
 			new (&_irqs[i * sizeof(Irq)]) Irq(i);
 		}
diff --git a/repos/base-hw/src/core/pic/arm_gic.h b/repos/base-hw/src/core/pic/arm_gic.h
index 78d141408..0afffe1bf 100644
--- a/repos/base-hw/src/core/pic/arm_gic.h
+++ b/repos/base-hw/src/core/pic/arm_gic.h
@@ -33,7 +33,7 @@ class Arm_gic::Pic
 {
 	public:
 
-		enum { MAX_INTERRUPT_ID = 1023 };
+		enum { NR_OF_IRQ = 1024 };
 
 	protected:
 
@@ -73,7 +73,7 @@ class Arm_gic::Pic
 			 * Interrupt group register
 			 */
 			struct Igroupr :
-				Register_array<0x80, 32, MAX_INTERRUPT_ID + 1, 1>
+				Register_array<0x80, 32, NR_OF_IRQ, 1>
 			{
 				struct Group_status : Bitfield<0, 1> { };
 			};
@@ -82,7 +82,7 @@ class Arm_gic::Pic
 			 * Interrupt set enable registers
 			 */
 			struct Isenabler :
-				Register_array<0x100, 32, MAX_INTERRUPT_ID + 1, 1, true>
+				Register_array<0x100, 32, NR_OF_IRQ, 1, true>
 			{
 				struct Set_enable : Bitfield<0, 1> { };
 			};
@@ -91,7 +91,7 @@ class Arm_gic::Pic
 			 * Interrupt clear enable registers
 			 */
 			struct Icenabler :
-				Register_array<0x180, 32, MAX_INTERRUPT_ID + 1, 1, true>
+				Register_array<0x180, 32, NR_OF_IRQ, 1, true>
 			{
 				struct Clear_enable : Bitfield<0, 1> { };
 			};
@@ -100,7 +100,7 @@ class Arm_gic::Pic
 			 * Interrupt priority level registers
 			 */
 			struct Ipriorityr :
-				Register_array<0x400, 32, MAX_INTERRUPT_ID + 1, 8>
+				Register_array<0x400, 32, NR_OF_IRQ, 8>
 			{
 				enum { GET_MIN = 0xff };
 
@@ -111,7 +111,7 @@ class Arm_gic::Pic
 			 * Interrupt processor target registers
 			 */
 			struct Itargetsr :
-				Register_array<0x800, 32, MAX_INTERRUPT_ID + 1, 8>
+				Register_array<0x800, 32, NR_OF_IRQ, 8>
 			{
 				enum { ALL = 0xff };
 
@@ -122,7 +122,7 @@ class Arm_gic::Pic
 			 * Interrupt configuration registers
 			 */
 			struct Icfgr :
-				Register_array<0xc00, 32, MAX_INTERRUPT_ID + 1, 2>
+				Register_array<0xc00, 32, NR_OF_IRQ, 2>
 			{
 				struct Edge_triggered : Bitfield<1, 1> { };
 			};
diff --git a/repos/base-hw/src/core/pic/imx31.h b/repos/base-hw/src/core/pic/imx31.h
index 96f96bf47..2d1c58708 100644
--- a/repos/base-hw/src/core/pic/imx31.h
+++ b/repos/base-hw/src/core/pic/imx31.h
@@ -126,7 +126,7 @@ namespace Imx31
 
 		public:
 
-			enum { MAX_INTERRUPT_ID = 63 };
+			enum { NR_OF_IRQ = 64 };
 
 			/**
 			 * Constructor, enables all interrupts
@@ -166,7 +166,7 @@ namespace Imx31
 			 * Validate request number 'i'
 			 */
 			bool valid(unsigned const i) const {
-				return i <= MAX_INTERRUPT_ID; }
+				return i < NR_OF_IRQ; }
 
 			/**
 			 * Unmask all interrupts
@@ -193,7 +193,7 @@ namespace Imx31
 			 */
 			void unmask(unsigned const interrupt_id, unsigned)
 			{
-				if (interrupt_id <= MAX_INTERRUPT_ID) {
+				if (interrupt_id < NR_OF_IRQ) {
 					write<Intennum>(interrupt_id);
 				}
 			}
@@ -202,7 +202,7 @@ namespace Imx31
 			 * Mask interrupt 'i'
 			 */
 			void mask(unsigned const i) {
-				if (i <= MAX_INTERRUPT_ID) write<Intdisnum>(i); }
+				if (i < NR_OF_IRQ) write<Intdisnum>(i); }
 
 			/**
 			 * Wether an interrupt is inter-processor interrupt of a processor
diff --git a/repos/base-hw/src/core/platform.cc b/repos/base-hw/src/core/platform.cc
index 9b9ecb5f2..7e15a683d 100644
--- a/repos/base-hw/src/core/platform.cc
+++ b/repos/base-hw/src/core/platform.cc
@@ -132,7 +132,7 @@ Platform::Platform()
 	           _core_only_ram_regions, get_page_size_log2());
 
 	/* make interrupts available to the interrupt allocator */
-	for (unsigned i = 0; i <= Kernel::Pic::MAX_INTERRUPT_ID; i++)
+	for (unsigned i = 0; i < Kernel::Pic::NR_OF_IRQ; i++)
 		_irq_alloc.add_range(i, 1);
 
 	/*
diff --git a/repos/base-hw/src/core/rpi/pic.h b/repos/base-hw/src/core/rpi/pic.h
index 8c74a72af..e6a1c6101 100644
--- a/repos/base-hw/src/core/rpi/pic.h
+++ b/repos/base-hw/src/core/rpi/pic.h
@@ -27,7 +27,7 @@ namespace Kernel
 	{
 		public:
 
-			enum { MAX_INTERRUPT_ID = 64 };
+			enum { NR_OF_IRQ = 64 };
 
 		private:
 
@@ -80,7 +80,7 @@ namespace Kernel
 				}
 
 				/* search for lowest set bit in pending masks */
-				for (unsigned i = 0; i < MAX_INTERRUPT_ID; i++) {
+				for (unsigned i = 0; i < NR_OF_IRQ; i++) {
 					if (!_is_pending(i, p1, p2))
 						continue;