hw: enable performance counter on ARMv6 and ARMv7
To actually enable the performance counter 'perf_counter' has to be added to the SPECS make variable. Fixes #893.
This commit is contained in:
Josef Söntgen
Norman Feske
parent
341290a266
commit
afdabe9df8
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@ -0,0 +1,31 @@
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/*
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* \brief Performance counter specific functions
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* \author Josef Soentgen
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* \date 2013-09-26
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _PERF_COUNTER_H_
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#define _PERF_COUNTER_H_
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namespace Kernel {
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class Perf_counter
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{
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public:
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void enable();
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};
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extern Perf_counter *perf_counter();
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}
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#endif /* _PERF_COUNTER_H_ */
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@ -0,0 +1,3 @@
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SRC_CC = perf_counter.cc
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vpath %.cc $(REP_DIR)/src/core/arm_v6
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@ -0,0 +1,3 @@
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SRC_CC = perf_counter.cc
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vpath %.cc $(REP_DIR)/src/core/arm_v7
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@ -0,0 +1,3 @@
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SRC_CC = perf_counter.cc
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vpath %.cc $(REP_DIR)/src/core/
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@ -0,0 +1 @@
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LIBS += enable_perf_counter
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@ -0,0 +1,125 @@
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/*
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* \brief Performance counter for ARMv6
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* \author Josef Soentgen
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* \date 2013-09-26
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*
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* The naming is based on ARM1176JZF-S Technical Reference Manual.
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* Genode includes */
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#include <util/register.h>
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/* base-hw includes */
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#include <kernel/perf_counter.h>
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using namespace Genode;
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/**
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* Performance Monitor Control Register
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*/
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struct Pmcr : Register<32>
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{
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struct E : Bitfield<0,1> { }; /* enable all counter */
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struct P : Bitfield<1,1> { }; /* count register reset */
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struct C : Bitfield<2,1> { }; /* cycle counter reset */
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struct D : Bitfield<3,1> { }; /* cycle counter divider */
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static access_t enable_and_reset()
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{
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return E::bits(1) |
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P::bits(1) |
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C::bits(1);
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}
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static access_t read()
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{
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access_t v;
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asm volatile("mrc p15, 0, %[v], c15, c12, 0" : [v]"=r"(v) :: );
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return v;
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}
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static void write(access_t const v)
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{
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asm volatile("mcr p15, 0, %[v], c15, c12, 0" :: [v]"r"(v) : );
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}
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};
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/**
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* System Validation Counter Register
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*/
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struct Sysvalcntrr : Register<32>
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{
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struct Resetcntr : Bitfield<0,1> { }; /* reset all counter */
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static access_t reset_counter()
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{
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return Resetcntr::bits(0);
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}
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static access_t read()
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{
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access_t v;
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asm volatile("mrc p15, 0, %[v], c15, c12, 1" : [v]"=r"(v) :: );
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return v;
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}
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static void write(access_t const v)
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{
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asm volatile("mcr p15, 0, %[v], c15, c12, 1" :: [v]"r"(v) : );
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}
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};
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/**
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* Secure User and Non-secure Access Validation Control Register
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*/
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struct Accvalctlr : Register<32>
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{
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struct V : Bitfield<0,1> { }; /* enable access in user-mode */
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static access_t enable_user_access()
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{
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return V::bits(1);
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}
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static access_t read()
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{
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access_t v;
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asm volatile("mrc p15, 0, %[v], c15, c9, 0" : [v]"=r"(v) :: );
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return v;
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}
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static void write(access_t const v)
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{
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asm volatile("mcr p15, 0, %[v], c15, c9, 0" :: [v]"r"(v) : );
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}
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};
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void Kernel::Perf_counter::enable()
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{
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/* enable counters and disable overflow interrupt. */
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Pmcr::access_t v = Pmcr::enable_and_reset() |
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Pmcr::D::bits(1); /* count every 64 cycles */
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Pmcr::write(v);
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Sysvalcntrr::write(Sysvalcntrr::reset_counter());
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/* enable user-mode access */
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Accvalctlr::write(Accvalctlr::enable_user_access());
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}
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Kernel::Perf_counter* Kernel::perf_counter()
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{
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static Kernel::Perf_counter inst;
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return &inst;
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}
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@ -0,0 +1,192 @@
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/*
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* \brief Performance counter ARMv7
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* \author Josef Soentgen
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* \date 2013-09-26
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*
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* The naming is based on ARM Architecture Reference Manual ARMv7-A.
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* Genode includes */
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#include <util/register.h>
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/* base-hw includes */
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#include <kernel/perf_counter.h>
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using namespace Genode;
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/**
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* Performance Monitor Control Register
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*/
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struct Pmcr : Register<32>
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{
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struct E : Bitfield<0,1> { }; /* enable all counters */
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struct P : Bitfield<1,1> { }; /* performance counter reset */
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struct C : Bitfield<2,1> { }; /* cycle counter reset */
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struct D : Bitfield<3,1> { }; /* clock divider */
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static access_t enable_and_reset()
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{
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return E::bits(1) |
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P::bits(1) |
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C::bits(1);
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}
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static access_t read()
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{
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access_t v;
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asm volatile("mrc p15, 0, %[v], c9, c12, 0" : [v]"=r"(v) :: );
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return v;
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}
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static void write(access_t const v)
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{
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asm volatile("mcr p15, 0, %[v], c9, c12, 0" :: [v]"r"(v) : );
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}
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};
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/**
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* Interrupt Enable Clear Register
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*/
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struct Pmintenclr : Register<32>
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{
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struct C : Bitfield<31,1> { }; /* disable cycle counter overflow interrupt request */
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struct P0 : Bitfield<0,1> { }; /* disable pmc0 overflow interrupt request */
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struct P1 : Bitfield<1,1> { }; /* disable pmc1 overflow interrupt reuqest */
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static access_t disable_overflow_intr()
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{
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return C::bits(1) |
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P0::bits(1) |
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P1::bits(1);
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}
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static access_t read()
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{
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access_t v;
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asm volatile("mrc p15, 0, %[v], c9, c14, 2" : [v]"=r"(v) :: );
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return v;
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}
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static void write(access_t const v)
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{
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asm volatile("mcr p15, 0, %[v], c9, c14, 2" :: [v]"r"(v) : );
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}
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};
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/**
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* Count Enable Set Register
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*/
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struct Pmcntenset : Register<32>
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{
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struct C : Bitfield<31,1> { }; /* cycle counter enable */
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struct P0 : Bitfield<0,1> { }; /* counter 0 enable */
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struct P1 : Bitfield<1,1> { }; /* counter 1 enable */
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struct P2 : Bitfield<2,1> { }; /* counter 2 enable */
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struct P3 : Bitfield<3,1> { }; /* counter 3 enable */
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static access_t enable_counter()
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{
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return C::bits(1) |
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P0::bits(1) |
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P1::bits(1) |
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P2::bits(1) |
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P3::bits(1);
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}
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static access_t read()
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{
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access_t v;
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asm volatile("mrc p15, 0, %[v], c9, c12, 1" : [v]"=r"(v) :: );
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return v;
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}
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static void write(access_t const v)
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{
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asm volatile("mcr p15, 0, %0, c9, c12, 1" :: [v]"r"(v) : );
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}
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};
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/**
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* Overflow Flag Status Register
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*/
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struct Pmovsr : Register<32>
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{
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struct C : Bitfield<31,1> { }; /* cycle counter overflow flag */
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struct P0 : Bitfield<0,1> { }; /* counter 0 overflow flag */
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struct P1 : Bitfield<1,1> { }; /* counter 1 overflow flag */
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static access_t clear_overflow_flags()
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{
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return C::bits(1) |
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P0::bits(1) |
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P1::bits(1);
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}
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static access_t read()
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{
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access_t v;
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asm volatile("mrc p15, 0, %[v], c9, c12, 3" : [v]"=r"(v) :: );
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return v;
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}
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static void write(access_t const v)
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{
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asm volatile("mcr p15, 0, %0, c9, c12, 3" :: [v]"r"(v) : );
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}
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};
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/**
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* User Enable Register
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*/
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struct Pmuseren : Register<32>
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{
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struct En : Bitfield<0,1> { }; /* enable user mode access */
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static access_t enable()
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{
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return En::bits(1);
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}
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static access_t read()
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{
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access_t v;
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asm volatile("mrc p15, 0, %[v], c9, c14, 0" : [v]"=r"(v) :: );
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return v;
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}
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static void write(access_t const v)
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{
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asm volatile("mcr p15, 0, %0, c9, c14, 0" :: [v]"r"(v) : );
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}
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};
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void Kernel::Perf_counter::enable()
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{
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/* program PMU and enable all counters */
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Pmcr::write(Pmcr::enable_and_reset());
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Pmcntenset::write(Pmcntenset::enable_counter());
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Pmovsr::write(Pmovsr::clear_overflow_flags());
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/* enable user-mode access to counters and disable overflow interrupt. */
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Pmuseren::write(Pmuseren::enable());
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Pmintenclr::write(Pmintenclr::disable_overflow_intr());
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}
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Kernel::Perf_counter* Kernel::perf_counter()
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{
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static Kernel::Perf_counter inst;
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return &inst;
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}
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@ -34,6 +34,7 @@
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/* base-hw includes */
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#include <singleton.h>
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#include <kernel/perf_counter.h>
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using namespace Kernel;
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@ -955,6 +956,9 @@ extern "C" void kernel()
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/* TrustZone initialization code */
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trustzone_initialization(pic());
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/* enable performance counter */
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perf_counter()->enable();
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/* switch to core address space */
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Cpu::init_virt_kernel(core()->tlb()->base(), core_id());
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@ -0,0 +1,25 @@
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/*
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* \brief Performance counter dummy
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* \author Josef Soentgen
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* \date 2013-09-26
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* base-hw includes */
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#include <kernel/perf_counter.h>
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void Kernel::Perf_counter::enable() { }
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Kernel::Perf_counter* Kernel::perf_counter()
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{
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static Kernel::Perf_counter inst;
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return &inst;
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}
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@ -11,7 +11,7 @@ TARGET = core
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CC_OPT += -DCORE_MAIN=_main
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# add library dependencies
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LIBS += base-common
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LIBS += base-common perf_counter
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# add include paths
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INC_DIR += $(REP_DIR)/src/core \
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