hw: refactor irq controllers

* name irq controller memory mapped I/O regions consistently
  in board descriptions
* move irq controller and timer memory mapped I/O region descriptions
  from cpu class to board class
* eliminate artificial distinction between flavors of ARM's GIC
* factor cpu local initialization out of ARM's GIC interface description,
  which is needed if the GIC is initialized differently e.g. for TrustZone

Ref #1405

repos/base-hw/lib/mk/cortex_a15/core.inc

@@ -6,6 +6,10 @@
 
 # add include paths
 INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a15
+INC_DIR += $(REP_DIR)/src/core/include/spec/arm_gic
+
+# add C++ sources
+SRC_CC += spec/arm_gic/pic.cc
 
 # include less specific configuration
 include $(REP_DIR)/lib/mk/arm_v7/core.inc

repos/base-hw/lib/mk/cortex_a9/core.inc

@@ -6,9 +6,11 @@
 
 # add include paths
 INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a9
+INC_DIR += $(REP_DIR)/src/core/include/spec/arm_gic
 
 # add C++ sources
 SRC_CC += spec/arm/cpu.cc
+SRC_CC += spec/arm_gic/pic.cc
 
 # include less specific configuration
 include $(REP_DIR)/lib/mk/arm_v7/core.inc

repos/base-hw/lib/mk/exynos5/core.mk

@@ -6,14 +6,11 @@
 
 # add include paths
 INC_DIR += $(REP_DIR)/src/core/include/spec/exynos5
-INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a15
-INC_DIR += $(REP_DIR)/src/core/include/spec/corelink_gic400
 
 # add C++ sources
 SRC_CC += spec/exynos5/platform_support.cc
 SRC_CC += spec/exynos5/cpu.cc
 SRC_CC += platform_services.cc
-SRC_CC += spec/arm_gic/pic.cc
 
 # include less specific configuration
 include $(REP_DIR)/lib/mk/cortex_a15/core.inc

repos/base-hw/lib/mk/platform_panda/core.mk

@@ -7,14 +7,11 @@
 
 # add include paths
 INC_DIR += $(REP_DIR)/src/core/include/spec/panda
-INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a9
 INC_DIR += $(REP_DIR)/src/core/include/spec/tl16c750
 
 # add C++ sources
 SRC_CC += platform_services.cc
 SRC_CC += spec/panda/platform_support.cc
-SRC_CC += spec/cortex_a9/pic.cc
-SRC_CC += spec/arm_gic/pic.cc
 
 # include less specific configuration
 include $(REP_DIR)/lib/mk/cortex_a9/core.inc

repos/base-hw/lib/mk/platform_pbxa9/core.mk

@@ -7,14 +7,11 @@
 
 # add include paths
 INC_DIR += $(REP_DIR)/src/core/include/spec/pbxa9
-INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a9
 INC_DIR += $(REP_DIR)/src/core/include/spec/pl011
 
 # add C++ sources
 SRC_CC += platform_services.cc
 SRC_CC += spec/pbxa9/platform_support.cc
-SRC_CC += spec/cortex_a9/pic.cc
-SRC_CC += spec/arm_gic/pic.cc
 
 # include less specific configuration
 include $(REP_DIR)/lib/mk/cortex_a9/core.inc

repos/base-hw/lib/mk/platform_vea9x4/core.mk

@@ -7,15 +7,12 @@
 
 # add include paths
 INC_DIR += $(REP_DIR)/src/core/include/spec/vea9x4
-INC_DIR += $(REP_DIR)/src/core/include/spec/cortex_a9
 INC_DIR += $(REP_DIR)/src/core/include/spec/pl011
 
 # add C++ sources
 SRC_CC += platform_services.cc
 SRC_CC += spec/vea9x4/platform_support.cc
 SRC_CC += spec/vea9x4/board.cc
-SRC_CC += spec/cortex_a9/pic.cc
-SRC_CC += spec/arm_gic/pic.cc
 
 # include less specific configuration
 include $(REP_DIR)/lib/mk/cortex_a9/core.inc

repos/base-hw/src/core/include/spec/arm_gic/pic.h

@@ -1,6 +1,7 @@
 /*
  * \brief  Programmable interrupt controller for core
  * \author Martin stein
+ * \author Stefan Kalkowski
  * \date   2011-10-26
  */
 
@@ -17,6 +18,9 @@
 /* Genode includes */
 #include <util/mmio.h>
 
+/* core includes */
+#include <board.h>
+
 namespace Genode
 {
 	/**
@@ -32,9 +36,12 @@ namespace Genode
 	/**
 	 * Programmable interrupt controller for core
 	 */
-	class Arm_gic;
+	class Pic;
 }
 
+namespace Kernel { using Pic = Genode::Pic; }
+
+
 class Genode::Arm_gic_distributor : public Mmio
 {
 	public:
@@ -168,7 +175,7 @@ class Genode::Arm_gic_cpu_interface : public Mmio
 		Arm_gic_cpu_interface(addr_t const base) : Mmio(base) { }
 };
 
-class Genode::Arm_gic
+class Genode::Pic
 {
 	protected:
 
@@ -205,26 +212,16 @@ class Genode::Arm_gic
 		/**
 		 * Constructor
 		 */
-		Arm_gic(addr_t const distr_base, addr_t const cpu_base)
+		Pic()
-		:
+		: _distr(Board::IRQ_CONTROLLER_DISTR_BASE),
-			_distr(distr_base), _cpui(cpu_base),
+		  _cpui (Board::IRQ_CONTROLLER_CPU_BASE),
 		  _max_irq(_distr.max_irq()),
 		  _last_request(spurious_id) { _init(); }
 
 		/**
 		 * Initialize CPU local interface of the controller
 		 */
-		void init_cpu_local()
+		void init_cpu_local();
-		{
-			/* disable the priority filter */
-			_cpui.write<Cpui::Pmr::Priority>(_distr.min_priority());
-
-			/* disable preemption of IRQ handling by other IRQs */
-			_cpui.write<Cpui::Bpr::Binary_point>(~0);
-
-			/* enable device */
-			_cpui.write<Cpui::Ctlr::Enable>(1);
-		}
 
 		/**
 		 * Try to take an IRQ and return wether it was successful

repos/base-hw/src/core/include/spec/corelink_gic400/pic.h

@@ -1,49 +0,0 @@
-/*
- * \brief  Programmable interrupt controller for core
- * \author Martin stein
- * \date   2013-01-22
- */
-
-/*
- * Copyright (C) 2013 Genode Labs GmbH
- *
- * This file is part of the Genode OS framework, which is distributed
- * under the terms of the GNU General Public License version 2.
- */
-
-#ifndef _PIC_H_
-#define _PIC_H_
-
-/* core includes */
-#include <spec/arm_gic/pic_support.h>
-#include <board.h>
-
-namespace Genode
-{
-	/**
-	 * Programmable interrupt controller for core
-	 */
-	class Pic;
-}
-
-class Genode::Pic : public Arm_gic
-{
-	private:
-
-		enum {
-			BASE       = Board::GIC_CPU_MMIO_BASE,
-			DISTR_BASE = BASE + 0x1000,
-			CPUI_BASE  = BASE + 0x2000,
-		};
-
-	public:
-
-		/**
-		 * Constructor
-		 */
-		Pic() : Arm_gic(DISTR_BASE, CPUI_BASE) { }
-};
-
-namespace Kernel { class Pic : public Genode::Pic { }; }
-
-#endif /* _PIC_H_ */

repos/base-hw/src/core/include/spec/cortex_a15/board_support.h

@@ -0,0 +1,41 @@
+/*
+ * \brief  Board driver definitions common to Cortex A15 SoCs
+ * \author Stefan Kalkowski
+ * \date   2015-02-09
+ */
+
+/*
+ * Copyright (C) 2015 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU General Public License version 2.
+ */
+
+#ifndef _SPEC__CORTEX_A15__BOARD_SUPPORT_H_
+#define _SPEC__CORTEX_A15__BOARD_SUPPORT_H_
+
+/* core includes */
+#include <drivers/board_base.h>
+
+namespace Cortex_a15
+{
+	class Board_base : public Genode::Board_base
+	{
+		private:
+
+			using Base = Genode::Board_base;
+
+		public:
+
+			enum
+			{
+				/* interrupt controller */
+				IRQ_CONTROLLER_DISTR_BASE = Base::IRQ_CONTROLLER_BASE + 0x1000,
+				IRQ_CONTROLLER_DISTR_SIZE = 0x1000,
+				IRQ_CONTROLLER_CPU_BASE   = Base::IRQ_CONTROLLER_BASE + 0x2000,
+				IRQ_CONTROLLER_CPU_SIZE   = 0x2000,
+			};
+	};
+}
+
+#endif /* _SPEC__CORTEX_A15__BOARD_SUPPORT_H_ */

repos/base-hw/src/core/include/spec/cortex_a9/board_support.h

@@ -0,0 +1,49 @@
+/*
+ * \brief  Board driver definitions common to Cortex A9 SoCs
+ * \author Stefan Kalkowski
+ * \date   2015-02-09
+ */
+
+/*
+ * Copyright (C) 2015 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU General Public License version 2.
+ */
+
+#ifndef _SPEC__CORTEX_A9__BOARD_H_
+#define _SPEC__CORTEX_A9__BOARD_H_
+
+/* core includes */
+#include <drivers/board_base.h>
+
+namespace Cortex_a9
+{
+	class Board_base : public Genode::Board_base
+	{
+		private:
+
+			using Base = Genode::Board_base;
+
+		public:
+
+			enum
+			{
+				/* interrupt controller */
+				IRQ_CONTROLLER_DISTR_BASE = Base::CORTEX_A9_PRIVATE_MEM_BASE
+				                            + 0x1000,
+				IRQ_CONTROLLER_DISTR_SIZE = 0x1000,
+				IRQ_CONTROLLER_CPU_BASE   = Base::CORTEX_A9_PRIVATE_MEM_BASE
+				                            + 0x100,
+				IRQ_CONTROLLER_CPU_SIZE   = 0x100,
+
+				/* timer */
+				PRIVATE_TIMER_MMIO_BASE   = Base::CORTEX_A9_PRIVATE_MEM_BASE
+				                            + 0x600,
+				PRIVATE_TIMER_MMIO_SIZE   = 0x10,
+				PRIVATE_TIMER_IRQ         = 29,
+			};
+	};
+}
+
+#endif /* _SPEC__CORTEX_A9__BOARD_H_ */

repos/base-hw/src/core/include/spec/cortex_a9/cpu.h

@@ -231,20 +231,6 @@ class Genode::Cpu : public Arm_v7
 				asm volatile ("mcr p15, 0, %0, c1, c0, 1" :: "r" (v) : ); }
 		};
 
-		enum
-		{
-			/* interrupt controller */
-			PL390_DISTRIBUTOR_MMIO_BASE = Board::CORTEX_A9_PRIVATE_MEM_BASE + 0x1000,
-			PL390_DISTRIBUTOR_MMIO_SIZE = 0x1000,
-			PL390_CPU_MMIO_BASE = Board::CORTEX_A9_PRIVATE_MEM_BASE + 0x100,
-			PL390_CPU_MMIO_SIZE = 0x100,
-
-			/* timer */
-			PRIVATE_TIMER_MMIO_BASE = Board::CORTEX_A9_PRIVATE_MEM_BASE + 0x600,
-			PRIVATE_TIMER_MMIO_SIZE = 0x10,
-			PRIVATE_TIMER_IRQ = 29,
-		};
-
 		/**
 		 * Constructor
 		 */

repos/base-hw/src/core/include/spec/cortex_a9/pic.h

@@ -1,47 +0,0 @@
-/*
- * \brief  Programmable interrupt controller for core
- * \author Martin stein
- * \date   2011-10-26
- */
-
-/*
- * Copyright (C) 2011-2013 Genode Labs GmbH
- *
- * This file is part of the Genode OS framework, which is distributed
- * under the terms of the GNU General Public License version 2.
- */
-
-#ifndef _PIC_H_
-#define _PIC_H_
-
-/* core includes */
-#include <spec/arm_gic/pic_support.h>
-#include <cpu.h>
-
-namespace Genode
-{
-	/**
-	 * Programmable interrupt controller for core
-	 */
-	class Pic;
-}
-
-class Genode::Pic : public Arm_gic
-{
-	public:
-
-		/**
-		 * Constructor
-		 */
-		Pic() : Arm_gic(Cpu::PL390_DISTRIBUTOR_MMIO_BASE,
-		                Cpu::PL390_CPU_MMIO_BASE) { }
-
-		/**
-		 * Mark interrupt 'i' unsecure
-		 */
-		void unsecure(unsigned const i);
-};
-
-namespace Kernel { class Pic : public Genode::Pic { }; }
-
-#endif /* _PIC_H_ */

repos/base-hw/src/core/include/spec/cortex_a9/timer.h

@@ -18,7 +18,7 @@
 #include <util/mmio.h>
 
 /* core includes */
-#include <cpu.h>
+#include <board.h>
 
 namespace Genode
 {
@@ -61,7 +61,7 @@ namespace Genode
 			/**
 			 * Constructor
 			 */
-			Timer() : Mmio(Cpu::PRIVATE_TIMER_MMIO_BASE)
+			Timer() : Mmio(Board::PRIVATE_TIMER_MMIO_BASE)
 			{
 				write<Control::Timer_enable>(0);
 			}
@@ -69,10 +69,8 @@ namespace Genode
 			/**
 			 * Return kernel name of timer interrupt
 			 */
-			static unsigned interrupt_id(unsigned)
+			static unsigned interrupt_id(unsigned) {
-			{
+				return Board::PRIVATE_TIMER_IRQ; }
-				return Cpu::PRIVATE_TIMER_IRQ;
-			}
 
 			/**
 			 * Start single timeout run

repos/base-hw/src/core/include/spec/exynos5/board.h

@@ -15,11 +15,11 @@
 #define _BOARD_H_
 
 /* core includes */
-#include <drivers/board_base.h>
+#include <spec/cortex_a15/board_support.h>
 
 namespace Genode
 {
-	class Board : public Board_base
+	class Board : public Cortex_a15::Board_base
 	{
 		public:
 

repos/base-hw/src/core/include/spec/imx53/board.h

@@ -15,7 +15,7 @@
 #define _BOARD_H_
 
 /* Genode includes */
-#include <platform/imx53/drivers/board_base.h>
+#include <drivers/board_base.h>
 #include <util/mmio.h>
 
 namespace Imx53

repos/base-hw/src/core/include/spec/imx53/pic.h

@@ -91,7 +91,7 @@ class Genode::Pic : public Mmio
 		/**
 		 * Constructor
 		 */
-		Pic() : Mmio(Board::TZIC_MMIO_BASE)
+		Pic() : Mmio(Board::IRQ_CONTROLLER_BASE)
 		{
 			for (unsigned i = 0; i < NR_OF_IRQ; i++) {
 				write<Intsec::Nonsecure>(1, i);

repos/base-hw/src/core/include/spec/panda/board.h

@@ -16,11 +16,11 @@
 
 /* core includes */
 #include <util/mmio.h>
-#include <drivers/board_base.h>
+#include <spec/cortex_a9/board_support.h>
 
 namespace Genode
 {
-	struct Board : Board_base
+	struct Board : Cortex_a9::Board_base
 	{
 		/**
 		 * L2 outer cache controller

repos/base-hw/src/core/include/spec/pbxa9/board.h

@@ -0,0 +1,34 @@
+/*
+ * \brief  Board driver for core
+ * \author Stefan Kalkowski
+ * \date   2015-02-09
+ */
+
+/*
+ * Copyright (C) 2015 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU General Public License version 2.
+ */
+
+#ifndef _SPEC__PBXA9__BOARD_H_
+#define _SPEC__PBXA9__BOARD_H_
+
+/* core includes */
+#include <spec/cortex_a9/board_support.h>
+
+namespace Genode
+{
+	class Board : public Cortex_a9::Board_base
+	{
+		public:
+
+			static void outer_cache_invalidate() { }
+			static void outer_cache_flush() { }
+			static void prepare_kernel() { }
+			static void secondary_cpus_ip(void * const ip) { }
+			static bool is_smp() { return false; }
+	};
+}
+
+#endif /* _SPEC__PBXA9__BOARD_H_ */

repos/base-hw/src/core/include/spec/vea9x4/board.h

@@ -15,11 +15,11 @@
 #define _BOARD_H_
 
 /* core includes */
-#include <drivers/board_base.h>
+#include <spec/cortex_a9/board_support.h>
 
 namespace Genode
 {
-	class Board : public Board_base
+	class Board : public Cortex_a9::Board_base
 	{
 		public:
 

repos/base-hw/src/core/include/trustzone.h

@@ -14,11 +14,10 @@
 #ifndef _CORE__INCLUDE__TRUSTZONE_H_
 #define _CORE__INCLUDE__TRUSTZONE_H_
 
+/* core includes */
+#include <pic.h>
+
 namespace Kernel {
-
-	class Pic;
-
-
 	void init_trustzone(Pic * pic);
 }
 

repos/base-hw/src/core/spec/arm_gic/pic.cc

@@ -16,7 +16,7 @@
 
 using namespace Genode;
 
-void Arm_gic::_init()
+void Pic::_init()
 {
 	/* disable device */
 	_distr.write<Distr::Ctlr::Enable>(0);
@@ -29,3 +29,16 @@ void Arm_gic::_init()
 	/* enable device */
 	_distr.write<Distr::Ctlr::Enable>(1);
 }
+
+
+void Pic::init_cpu_local()
+{
+	/* disable the priority filter */
+	_cpui.write<Cpui::Pmr::Priority>(_distr.min_priority());
+
+	/* disable preemption of IRQ handling by other IRQs */
+	_cpui.write<Cpui::Bpr::Binary_point>(~0);
+
+	/* enable device */
+	_cpui.write<Cpui::Ctlr::Enable>(1);
+}

repos/base-hw/src/core/spec/cortex_a9/pic.cc

@@ -1,19 +0,0 @@
-/*
- * \brief  Programmable interrupt controller for core
- * \author Martin stein
- * \date   2011-10-26
- */
-
-/*
- * Copyright (C) 2011-2013 Genode Labs GmbH
- *
- * This file is part of the Genode OS framework, which is distributed
- * under the terms of the GNU General Public License version 2.
- */
-
-/* core includes */
-#include <pic.h>
-
-using namespace Genode;
-
-void Pic::unsecure(unsigned const i) { }

repos/base-hw/src/core/spec/exynos5/platform_support.cc

@@ -45,7 +45,7 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i)
 {
 	static Native_region _regions[] =
 	{
-		{ Board::GIC_CPU_MMIO_BASE, Board::GIC_CPU_MMIO_SIZE },
+		{ Board::IRQ_CONTROLLER_BASE, Board::IRQ_CONTROLLER_SIZE },
 		{ Board::MCT_MMIO_BASE, Board::MCT_MMIO_SIZE },
 		{ Board::UART_2_MMIO_BASE, 0x1000 },
 	};

repos/base-hw/src/core/spec/imx53/platform_support.cc

@@ -53,7 +53,7 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i)
 		{ Board::EPIT_1_MMIO_BASE, Board::EPIT_1_MMIO_SIZE },
 
 		/* interrupt controller */
-		{ Board::TZIC_MMIO_BASE, Board::TZIC_MMIO_SIZE },
+		{ Board::IRQ_CONTROLLER_BASE, Board::IRQ_CONTROLLER_SIZE },
 	};
 	return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
 }

repos/base-hw/src/core/spec/imx53/trustzone/platform_support.cc

@@ -92,7 +92,7 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i)
 		{ Board::EPIT_1_MMIO_BASE, Board::EPIT_1_MMIO_SIZE },
 
 		/* interrupt controller */
-		{ Board::TZIC_MMIO_BASE, Board::TZIC_MMIO_SIZE },
+		{ Board::IRQ_CONTROLLER_BASE, Board::IRQ_CONTROLLER_SIZE },
 
 		/* central security unit */
 		{ Board::CSU_BASE, Board::CSU_SIZE },

repos/base/include/platform/imx53/drivers/board_base.h

@@ -71,8 +71,8 @@ namespace Genode
 			GPIO7_IRQL         = 107,
 			GPIO7_IRQH         = 108,
 
-			TZIC_MMIO_BASE     = 0x0fffc000,
+			IRQ_CONTROLLER_BASE = 0x0fffc000,
-			TZIC_MMIO_SIZE     = 0x00004000,
+			IRQ_CONTROLLER_SIZE = 0x00004000,
 
 			AIPS_1_MMIO_BASE   = 0x53f00000,
 			AIPS_2_MMIO_BASE   = 0x63f00000,

repos/base/include/platform_exynos5/board_base.h

@@ -36,8 +36,8 @@ class Genode::Exynos5
 			MMIO_0_SIZE = 0x10000000,
 
 			/* interrupt controller */
-			GIC_CPU_MMIO_BASE = 0x10480000,
+			IRQ_CONTROLLER_BASE = 0x10480000,
-			GIC_CPU_MMIO_SIZE = 0x00010000,
+			IRQ_CONTROLLER_SIZE = 0x00010000,
 
 			/* UART */
 			UART_2_MMIO_BASE = 0x12C20000,