From a361fbd2bcf9a01d135187fffa8fd96d5e6f29d0 Mon Sep 17 00:00:00 2001
From: Reto Buerki <reet@codelabs.ch>
Date: Thu, 26 Feb 2015 11:07:32 +0100
Subject: [PATCH] hw_x86_64: Move ISR entries to mode transition page

This is needed to make them available for non-core threads which
initially only have the mode transition page mapped.
---
 repos/base-hw/src/core/spec/x86_64/idt.cc     | 16 +++---
 .../src/core/spec/x86_64/mode_transition.s    | 56 +++++++++++++++++--
 2 files changed, 61 insertions(+), 11 deletions(-)

diff --git a/repos/base-hw/src/core/spec/x86_64/idt.cc b/repos/base-hw/src/core/spec/x86_64/idt.cc
index 9701305a2..c9f46b44c 100644
--- a/repos/base-hw/src/core/spec/x86_64/idt.cc
+++ b/repos/base-hw/src/core/spec/x86_64/idt.cc
@@ -2,8 +2,6 @@
 
 using namespace Genode;
 
-extern uint64_t _isr_array[];
-
 class Descriptor
 {
 	private:
@@ -19,14 +17,18 @@ __attribute__((aligned(8))) Idt::gate Idt::_table[SIZE_IDT];
 
 void Idt::setup()
 {
-	uint64_t *isrs = _isr_array;
+	/* TODO: Calculate from _mt_isrs label */
+	uint64_t base = 0;
 
-	for (unsigned vec = 0; vec < SIZE_IDT; vec++, isrs++) {
-		_table[vec].offset_15_00 = *isrs & 0xffff;
+	for (unsigned vec = 0; vec < SIZE_IDT; vec++) {
+		/* ISRs are padded to 4 bytes */
+		base = vec * 0xc;
+
+		_table[vec].offset_15_00 = base & 0xffff;
 		_table[vec].segment_sel  = 8;
 		_table[vec].flags        = 0x8e00;
-		_table[vec].offset_31_16 = (*isrs >> 16) & 0xffff;
-		_table[vec].offset_63_32 = (*isrs >> 32) & 0xffff;
+		_table[vec].offset_31_16 = (base >> 16) & 0xffff;
+		_table[vec].offset_63_32 = (base >> 32) & 0xffff;
 	}
 
 	/* Set DPL of syscall entry to 3 */
diff --git a/repos/base-hw/src/core/spec/x86_64/mode_transition.s b/repos/base-hw/src/core/spec/x86_64/mode_transition.s
index ff41034a5..91d8f72b2 100644
--- a/repos/base-hw/src/core/spec/x86_64/mode_transition.s
+++ b/repos/base-hw/src/core/spec/x86_64/mode_transition.s
@@ -29,6 +29,25 @@
 .set TRAPNO_OFFSET,  19 * 8
 .set CR3_OFFSET,     21 * 8
 
+.macro _isr_entry
+	.align 4, 0x90
+.endm
+
+.macro _exception vector
+	_isr_entry
+	push $0
+	push $\vector
+	jmp _mt_kernel_entry_pic
+.endm
+
+.macro _exception_with_code vector
+	_isr_entry
+	nop
+	nop
+	push $\vector
+	jmp _mt_kernel_entry_pic
+.endm
+
 .section .text
 
 	/*
@@ -44,6 +63,39 @@
 	.global _mt_begin
 	_mt_begin:
 
+	/*
+	 * On user exceptions the CPU has to jump to one of the following
+	 * Interrupt Service Routines (ISRs) to switch to a kernel context.
+	 */
+	.global _mt_isrs
+	_mt_isrs:
+	_exception              0
+	_exception              1
+	_exception              2
+	_exception              3
+	_exception              4
+	_exception              5
+	_exception              6
+	_exception              7
+	_exception_with_code    8
+	_exception              9
+	_exception_with_code    10
+	_exception_with_code    11
+	_exception_with_code    12
+	_exception_with_code    13
+	_exception_with_code    14
+	_exception              15
+	_exception              16
+	_exception_with_code    17
+	_exception              18
+	_exception              19
+
+	.set vec, 20
+	.rept 236
+	_exception              vec
+	.set vec, vec + 1
+	.endr
+
 	/* space for a copy of the kernel context */
 	.p2align 2
 	.global _mt_master_context_begin
@@ -67,10 +119,6 @@
 	_mt_buffer:
 	.space BUFFER_SIZE
 
-	/*
-	 * On user exceptions the CPU has to jump to one of the following
-	 * seven entry vectors to switch to a kernel context.
-	 */
 	.global _mt_kernel_entry_pic
 	_mt_kernel_entry_pic: