Martin Stein
Norman Feske
parent
65136c2289
commit
a0d182e25a
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@ -66,6 +66,7 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i)
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static Native_region _regions[] =
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{
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{ Board::GIC_CPU_MMIO_BASE, Board::GIC_CPU_MMIO_SIZE },
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{ Board::MCT_MMIO_BASE, Board::MCT_MMIO_SIZE },
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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@ -0,0 +1,3 @@
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INC_DIR += $(REP_DIR)/src/drivers/timer/hw $(REP_DIR)/src/drivers/timer/hw/exynos5
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include $(REP_DIR)/lib/mk/timer.inc
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@ -0,0 +1,211 @@
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/*
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* \brief Basic driver behind platform timer
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* \author Martin stein
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* \date 2013-04-04
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _HW__EXYNOS5__PLATFORM_TIMER_BASE_H_
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#define _HW__EXYNOS5__PLATFORM_TIMER_BASE_H_
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/* Genode includes */
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#include <io_mem_session/connection.h>
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#include <irq_session/connection.h>
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#include <drivers/board_base.h>
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#include <util/mmio.h>
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namespace Genode
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{
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/**
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* Exynos 5250 pulse width modulation timer
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*/
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class Pwm : public Mmio
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{
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enum { PRESCALER = 2 };
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/**
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* Timer configuration 0
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*/
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struct Cfg0 : Register<0x0, 32>
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{
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struct Prescaler0 : Bitfield<0, 8>
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{
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enum { DEFAULT = PRESCALER - 1 };
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};
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};
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/**
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* Timer configuration 1
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*/
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struct Cfg1 : Register<0x4, 32>
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{
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struct Div0 : Bitfield<0, 4> { enum { DISABLE = 0 }; };
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};
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/**
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* Timer control
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*/
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struct Con : Register<0x8, 32>
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{
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struct Enable0 : Bitfield<0, 1> { };
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struct Update0 : Bitfield<1, 1> { };
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struct Invert_tout0 : Bitfield<2, 1> { };
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struct Auto_reload0 : Bitfield<3, 1> { };
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struct Deadzone_en : Bitfield<4, 1> { };
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/**
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* Initialization value
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*/
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static access_t init_value()
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{
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return Invert_tout0::bits(0) |
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Auto_reload0::bits(1) |
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Deadzone_en::bits(0);
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}
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};
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/**
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* Timer 0 count buffer
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*/
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struct Cntb0 : Register<0xc, 32> { };
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/**
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* Timer 0 compare buffer
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*/
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struct Cmpb0 : Register<0x10, 32> { };
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/**
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* Timer 0 count observation
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*/
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struct Cnto0 : Register<0x14, 32> { };
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/**
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* Timer IRQ control and status
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*/
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struct Int : Register<0x44, 32>
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{
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struct En0 : Bitfield<0, 1> { };
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struct En1 : Bitfield<1, 1> { };
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struct En2 : Bitfield<2, 1> { };
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struct En3 : Bitfield<3, 1> { };
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struct En4 : Bitfield<4, 1> { };
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struct Stat0 : Bitfield<5, 1> { };
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/**
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* Initialization value
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*/
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static access_t init_value()
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{
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return En0::bits(1) |
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En1::bits(0) |
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En2::bits(0) |
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En3::bits(0) |
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En4::bits(0);
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}
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};
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/**
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* Timer tics per microsecond
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*/
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static float tics_per_us() {
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return (float)Board_base::PWM_CLOCK / PRESCALER / 1000 / 1000; }
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/**
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* Microseconds per timer tic
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*/
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static float us_per_tic() { return (float)1 / tics_per_us(); }
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public:
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/**
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* Constructor
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*
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* \param base MMIO base
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*/
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Pwm(addr_t const base) : Mmio(base)
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{
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write<Cfg0::Prescaler0>(Cfg0::Prescaler0::DEFAULT);
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write<Cfg1::Div0>(Cfg1::Div0::DISABLE);
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write<Int>(Int::init_value());
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write<Con>(Con::init_value());
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write<Cmpb0>(0);
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}
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/**
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* Count down 'value', raise IRQ output, wrap counter and continue
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*/
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void run_and_wrap(unsigned long value)
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{
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write<Cntb0>(value);
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write<Con::Enable0>(0);
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write<Con::Update0>(1);
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write<Con::Update0>(0);
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write<Int::Stat0>(1);
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write<Cntb0>(max_value());
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write<Con::Enable0>(1);
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}
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/**
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* Maximum timeout value
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*/
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unsigned long max_value() const { return (Cntb0::access_t)~0; }
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/**
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* Translate timer tics to microseconds
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*/
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unsigned long tics_to_us(unsigned long const tics) const
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{
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float const us = tics * us_per_tic();
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return (unsigned long)us;
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}
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/**
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* Translate microseconds to timer tics
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*/
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unsigned long us_to_tics(unsigned long const us)
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{
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float const tics = us * tics_per_us();
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return (unsigned long)tics;
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}
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/**
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* Sample the timer counter and according wrapped status
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*/
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unsigned long value(bool & wrapped) const
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{
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unsigned long v = read<Cnto0>();
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wrapped = (bool)read<Int::Stat0>();
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return wrapped ? read<Cnto0>() : v;
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}
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};
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}
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/**
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* Basic driver behind platform timer
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*/
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class Platform_timer_base : public Genode::Io_mem_connection,
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public Genode::Pwm
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{
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public:
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enum { IRQ = Genode::Board_base::PWM_IRQ_0 };
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/**
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* Constructor
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*/
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Platform_timer_base()
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: Io_mem_connection(Genode::Board_base::PWM_MMIO_BASE,
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Genode::Board_base::PWM_MMIO_SIZE),
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Genode::Pwm((Genode::addr_t)Genode::env()->rm_session()
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->attach(dataspace()))
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{ }
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};
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#endif /* _HW__EXYNOS5__PLATFORM_TIMER_BASE_H_ */
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