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Define board declarations in a more generic fashion 

By naming all board declaration (previously in base/include/drivers/board) the
same way, and putting them in platform-specific include-pathes, we save additional
declaration redirection in the base-hw kernel, and in driver definitions.
This commit is contained in:
Stefan Kalkowski 2012-09-28 15:47:27 +02:00 committed by Norman Feske
parent d3902e8538
commit 96d45c1159
14 changed files with 50 additions and 223 deletions
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4
base-hw/include/pl011/drivers/serial_log.h
View File

@ -33,8 +33,8 @@ namespace Genode
* \param baud_rate targeted transfer baud-rate
*/
Serial_log(unsigned const baud_rate) :
Pl011_base(Board::LOG_PL011_MMIO_BASE,
Board::LOG_PL011_CLOCK, baud_rate)
Pl011_base(Board::PL011_0_MMIO_BASE,
Board::PL011_0_CLOCK, baud_rate)
{ }
};
}

37
base-hw/include/platform/panda_a2/drivers/board.h
View File

@ -1,37 +0,0 @@
/**
* \brief Motherboard driver specific for the PandaBoard A2
* \author Martin Stein
* \date 2012-03-08
*/
/*
* Copyright (C) 2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__PLATFORM__PANDA_A2__DRIVERS__BOARD_H_
#define _INCLUDE__PLATFORM__PANDA_A2__DRIVERS__BOARD_H_
/* Genode includes */
#include <drivers/board/panda_a2.h>
namespace Genode
{
/**
* Provide specific board driver
*/
class Board : public Panda_a2
{
public:
enum {
LOG_TL16C750_MMIO_BASE = TL16C750_3_MMIO_BASE,
LOG_TL16C750_CLOCK = TL16C750_3_CLOCK,
};
};
}
#endif /* _INCLUDE__PLATFORM__PANDA_A2__DRIVERS__BOARD_H_ */

38
base-hw/include/platform/pbxa9/drivers/board.h
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@ -1,38 +0,0 @@
/**
* \brief Motherboard driver specific for the Realview PBXA9
* \author Martin Stein
* \date 2011-11-03
*/
/*
* Copyright (C) 2011-2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__PLATFORM__PBXA9__DRIVERS__BOARD_H_
#define _INCLUDE__PLATFORM__PBXA9__DRIVERS__BOARD_H_
/* Genode includes */
#include <drivers/board/pbxa9.h>
#include <base/native_types.h>
namespace Genode
{
/**
* Provide specific board driver
*/
class Board : public Pbxa9
{
public:
enum {
LOG_PL011_MMIO_BASE = PL011_0_MMIO_BASE,
LOG_PL011_CLOCK = PL011_0_CLOCK,
};
};
}
#endif /* _INCLUDE__PLATFORM__PBXA9__DRIVERS__BOARD_H_ */

37
base-hw/include/platform/vea9x4/drivers/board.h
View File

@ -1,37 +0,0 @@
/**
* \brief Provide specific board driver
* \author Martin Stein
* \date 2011-11-03
*/
/*
* Copyright (C) 2011-2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__PLATFORM__VEA9X4__DRIVERS__BOARD_H_
#define _INCLUDE__PLATFORM__VEA9X4__DRIVERS__BOARD_H_
/* Genode inlcudes */
#include <drivers/board/vea9x4.h>
namespace Genode
{
/**
* Provide specific board driver
*/
class Board : public Vea9x4
{
public:
enum {
LOG_PL011_MMIO_BASE = PL011_0_MMIO_BASE,
LOG_PL011_CLOCK = PL011_0_CLOCK,
};
};
}
#endif /* _INCLUDE__PLATFORM__VEA9X4__DRIVERS__BOARD_H_ */

4
base-hw/include/tl16c750/drivers/serial_log.h
View File

@ -33,8 +33,8 @@ namespace Genode
* \param baud_rate targeted transfer baud-rate
*/
Serial_log(unsigned const baud_rate) :
Tl16c750_base(Board::LOG_TL16C750_MMIO_BASE,
Board::LOG_TL16C750_CLOCK, baud_rate)
Tl16c750_base(Board::TL16C750_3_MMIO_BASE,
Board::TL16C750_3_CLOCK, baud_rate)
{ }
};
}

18
base-hw/src/core/panda_a2/platform_support.cc
View File

@ -12,7 +12,7 @@
*/
/* Genode includes */
#include <drivers/board/panda_a2.h>
#include <drivers/board.h>
#include <drivers/cpu/cortex_a9/core.h>
#include <drivers/pic/pl390_base.h>
@ -26,8 +26,8 @@ Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Panda_a2::EMIF1_EMIF2_CS0_SDRAM_BASE,
Panda_a2::EMIF1_EMIF2_CS0_SDRAM_SIZE }
{ Board::EMIF1_EMIF2_CS0_SDRAM_BASE,
Board::EMIF1_EMIF2_CS0_SDRAM_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -51,7 +51,7 @@ Native_region * Platform::_core_only_irq_regions(unsigned const i)
{ Cortex_a9::PRIVATE_TIMER_IRQ, 1 },
/* core UART */
{ Panda_a2::TL16C750_3_IRQ, 1 }
{ Board::TL16C750_3_IRQ, 1 }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -61,8 +61,8 @@ Native_region * Platform::_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Panda_a2::L4_PER_BASE, Panda_a2::L4_PER_SIZE },
{ Panda_a2::L4_CFG_BASE, Panda_a2::L4_CFG_SIZE }
{ Board::L4_PER_BASE, Board::L4_PER_SIZE },
{ Board::L4_CFG_BASE, Board::L4_CFG_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -73,11 +73,11 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i)
static Native_region _regions[] =
{
/* core timer and PIC */
{ Panda_a2::CORTEX_A9_PRIVATE_MEM_BASE,
Panda_a2::CORTEX_A9_PRIVATE_MEM_SIZE },
{ Board::CORTEX_A9_PRIVATE_MEM_BASE,
Board::CORTEX_A9_PRIVATE_MEM_SIZE },
/* core UART */
{ Panda_a2::TL16C750_3_MMIO_BASE, Panda_a2::TL16C750_3_MMIO_SIZE }
{ Board::TL16C750_3_MMIO_BASE, Board::TL16C750_3_MMIO_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}

14
base-hw/src/core/pbxa9/platform_support.cc
View File

@ -12,7 +12,7 @@
*/
/* Genode includes */
#include <drivers/board/pbxa9.h>
#include <drivers/board.h>
#include <drivers/cpu/cortex_a9/core.h>
#include <drivers/pic/pl390_base.h>
@ -26,7 +26,7 @@ Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Pbxa9::NORTHBRIDGE_DDR_0_BASE, Pbxa9::NORTHBRIDGE_DDR_0_SIZE }
{ Board::NORTHBRIDGE_DDR_0_BASE, Board::NORTHBRIDGE_DDR_0_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -50,7 +50,7 @@ Native_region * Platform::_core_only_irq_regions(unsigned const i)
{ Cortex_a9::PRIVATE_TIMER_IRQ, 1 },
/* core UART */
{ Pbxa9::PL011_0_IRQ, 1 }
{ Board::PL011_0_IRQ, 1 }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -60,8 +60,8 @@ Native_region * Platform::_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Pbxa9::SOUTHBRIDGE_APB_BASE, Pbxa9::SOUTHBRIDGE_APB_SIZE },
{ Pbxa9::NORTHBRIDGE_AHB_BASE, Pbxa9::NORTHBRIDGE_AHB_SIZE }
{ Board::SOUTHBRIDGE_APB_BASE, Board::SOUTHBRIDGE_APB_SIZE },
{ Board::NORTHBRIDGE_AHB_BASE, Board::NORTHBRIDGE_AHB_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -72,10 +72,10 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i)
static Native_region _regions[] =
{
/* core timer and PIC */
{ Pbxa9::CORTEX_A9_PRIVATE_MEM_BASE, Pbxa9::CORTEX_A9_PRIVATE_MEM_SIZE },
{ Board::CORTEX_A9_PRIVATE_MEM_BASE, Board::CORTEX_A9_PRIVATE_MEM_SIZE },
/* core UART */
{ Pbxa9::PL011_0_MMIO_BASE, Pbxa9::PL011_0_MMIO_SIZE }
{ Board::PL011_0_MMIO_BASE, Board::PL011_0_MMIO_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}

16
base-hw/src/core/vea9x4/platform_support.cc
View File

@ -12,7 +12,7 @@
*/
/* Genode includes */
#include <drivers/board/vea9x4.h>
#include <drivers/board.h>
#include <drivers/cpu/cortex_a9/core.h>
#include <drivers/pic/pl390_base.h>
@ -26,7 +26,7 @@ Native_region * Platform::_ram_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Vea9x4::LOCAL_DDR2_BASE, Vea9x4::LOCAL_DDR2_SIZE }
{ Board::LOCAL_DDR2_BASE, Board::LOCAL_DDR2_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -50,7 +50,7 @@ Native_region * Platform::_core_only_irq_regions(unsigned const i)
{ Cortex_a9::PRIVATE_TIMER_IRQ, 1 },
/* Core UART */
{ Vea9x4::PL011_0_IRQ, 1 }
{ Board::PL011_0_IRQ, 1 }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -60,8 +60,8 @@ Native_region * Platform::_mmio_regions(unsigned const i)
{
static Native_region _regions[] =
{
{ Vea9x4::SMB_CS7_BASE, Vea9x4::SMB_CS7_SIZE },
{ Vea9x4::SMB_CS0_TO_CS6_BASE, Vea9x4::SMB_CS0_TO_CS6_SIZE }
{ Board::SMB_CS7_BASE, Board::SMB_CS7_SIZE },
{ Board::SMB_CS0_TO_CS6_BASE, Board::SMB_CS0_TO_CS6_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}
@ -72,11 +72,11 @@ Native_region * Platform::_core_only_mmio_regions(unsigned const i)
static Native_region _regions[] =
{
/* Core timer and PIC */
{ Vea9x4::CORTEX_A9_PRIVATE_MEM_BASE,
Vea9x4::CORTEX_A9_PRIVATE_MEM_SIZE },
{ Board::CORTEX_A9_PRIVATE_MEM_BASE,
Board::CORTEX_A9_PRIVATE_MEM_SIZE },
/* Core UART */
{ Vea9x4::PL011_0_MMIO_BASE, Vea9x4::PL011_0_MMIO_SIZE }
{ Board::PL011_0_MMIO_BASE, Board::PL011_0_MMIO_SIZE }
};
return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
}

8
base/include/drivers/board/panda_a2.h → base/include/platform/panda_a2/drivers/board.h
View File

@ -11,15 +11,15 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__DRIVERS__BOARD__PANDA_A2_H_
#define _INCLUDE__DRIVERS__BOARD__PANDA_A2_H_
#ifndef _INCLUDE__DRIVERS__BOARD_H_
#define _INCLUDE__DRIVERS__BOARD_H_
namespace Genode
{
/**
* Driver for the OMAP4 PandaBoard revision A2
*/
struct Panda_a2
struct Board
{
enum
{
@ -51,5 +51,5 @@ namespace Genode
};
}
#endif /* _INCLUDE__DRIVERS__BOARD__PANDA_A2_H_ */
#endif /* _INCLUDE__DRIVERS__BOARD_H_ */

31
base/include/drivers/board/pbxa9.h → base/include/platform/pbxa9/drivers/board.h
View File

@ -11,15 +11,15 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__DRIVERS__BOARD__PBXA9_H_
#define _INCLUDE__DRIVERS__BOARD__PBXA9_H_
#ifndef _INCLUDE__DRIVERS__BOARD_H_
#define _INCLUDE__DRIVERS__BOARD_H_
namespace Genode
{
/**
* Driver for the Realview PBXA9 board
*/
struct Pbxa9
struct Board
{
enum
{
@ -51,28 +51,13 @@ namespace Genode
PL011_0_IRQ = 44,
/* timer */
SP804_0_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x11000,
SP804_0_MMIO_SIZE = 4*1024,
SP804_0_IRQ = 36,
SP804_0_CLOCK = 1*1000*1000,
SP804_1_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x12000,
SP804_1_MMIO_SIZE = 4*1024,
SP804_1_IRQ = 37,
SP804_1_CLOCK = 1*1000*1000,
SP804_2_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x18000,
SP804_2_MMIO_SIZE = 4*1024,
SP804_2_IRQ = 73,
SP804_2_CLOCK = 1*1000*1000,
SP804_3_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x19000,
SP804_3_MMIO_SIZE = 4*1024,
SP804_3_IRQ = 74,
SP804_3_CLOCK = 1*1000*1000,
SP804_0_1_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x11000,
SP804_0_1_MMIO_SIZE = 4*1024,
SP804_0_1_IRQ = 36,
SP804_0_1_CLOCK = 1*1000*1000,
};
};
}
#endif /* _INCLUDE__DRIVERS__BOARD__PBXA9_H_ */
#endif /* _INCLUDE__DRIVERS__BOARD_H_ */

8
base/include/drivers/board/vea9x4.h → base/include/platform/vea9x4/drivers/board.h
View File

@ -11,8 +11,8 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__DRIVERS__BOARD__VEA9X4_H_
#define _INCLUDE__DRIVERS__BOARD__VEA9X4_H_
#ifndef _INCLUDE__DRIVERS__BOARD_H_
#define _INCLUDE__DRIVERS__BOARD_H_
namespace Genode
{
@ -21,7 +21,7 @@ namespace Genode
*
* Implies the uATX motherboard and the CoreTile Express A9X4 daughterboard
*/
struct Vea9x4
struct Board
{
enum
{
@ -59,5 +59,5 @@ namespace Genode
};
}
#endif /* _INCLUDE__DRIVERS__BOARD__VEA9X4_H_ */
#endif /* _INCLUDE__DRIVERS__BOARD_H_ */

10
os/src/drivers/timer/hw/pbxa9/platform_timer_base.h
View File

@ -17,25 +17,25 @@
/* Genode includes */
#include <io_mem_session/connection.h>
#include <drivers/timer/sp804_base.h>
#include <drivers/board/pbxa9.h>
#include <drivers/board.h>
/**
* Platform-timer base specific for base-hw and PBXA9
*/
class Platform_timer_base :
public Genode::Io_mem_connection,
public Genode::Sp804_base<Genode::Pbxa9::SP804_0_CLOCK>
public Genode::Sp804_base<Genode::Board::SP804_0_1_CLOCK>
{
public:
enum { IRQ = Genode::Pbxa9::SP804_0_IRQ };
enum { IRQ = Genode::Board::SP804_0_1_IRQ };
/**
* Constructor
*/
Platform_timer_base() :
Io_mem_connection(Genode::Pbxa9::SP804_0_MMIO_BASE,
Genode::Pbxa9::SP804_0_MMIO_SIZE),
Io_mem_connection(Genode::Board::SP804_0_1_MMIO_BASE,
Genode::Board::SP804_0_1_MMIO_SIZE),
Sp804_base((Genode::addr_t)Genode::env()->rm_session()->
attach(dataspace()))

46
os/src/drivers/timer/hw/vea9x4/platform_timer_base.h
View File

@ -1,46 +0,0 @@
/*
* \brief Platform-timer base specific for base-hw and VEA9X4
* \author Martin Stein
* \date 2012-05-03
*/
/*
* Copyright (C) 2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _OS__SRC__DRIVERS__TIMER__HW__VEA9X4__PLATFORM_TIMER_BASE_H_
#define _OS__SRC__DRIVERS__TIMER__HW__VEA9X4__PLATFORM_TIMER_BASE_H_
/* Genode includes */
#include <io_mem_session/connection.h>
#include <drivers/timer/sp804_base.h>
#include <drivers/board/vea9x4.h>
/**
* Platform-timer base specific for base-hw and VEA9X4
*/
class Platform_timer_base :
public Genode::Io_mem_connection,
public Genode::Sp804_base<Genode::Vea9x4::SP804_0_1_CLOCK>
{
public:
enum { IRQ = Genode::Vea9x4::SP804_0_1_IRQ };
/**
* Constructor
*/
Platform_timer_base() :
Io_mem_connection(Genode::Vea9x4::SP804_0_1_MMIO_BASE,
Genode::Vea9x4::SP804_0_1_MMIO_SIZE),
Sp804_base((Genode::addr_t)Genode::env()->rm_session()->
attach(dataspace()))
{ }
};
#endif /* _OS__SRC__DRIVERS__TIMER__HW__VEA9X4__PLATFORM_TIMER_BASE_H_ */

2
os/src/drivers/timer/hw/vea9x4/target.mk
View File

@ -17,7 +17,7 @@ REQUIRES += hw_vea9x4
LIBS += cxx server env alarm
# Add include paths
INC_DIR += $(PRG_DIR) $(PRG_DIR)/../ $(PRG_DIR)/../../nova/
INC_DIR += $(PRG_DIR)/../ $(PRG_DIR)/../pbxa9 $(PRG_DIR)/../../nova/
# Declare source paths
vpath main.cc $(PRG_DIR)/../..