diff --git a/repos/base-hw/src/core/include/spec/x86/cpu.h b/repos/base-hw/src/core/include/spec/x86/cpu.h
index 8ef89302c..b8b02e35e 100644
--- a/repos/base-hw/src/core/include/spec/x86/cpu.h
+++ b/repos/base-hw/src/core/include/spec/x86/cpu.h
@@ -275,6 +275,13 @@ class Genode::Cpu
 			Kernel::Call_arg user_arg_6() const { return r10; }
 			Kernel::Call_arg user_arg_7() const { return r11; }
 
+			/* Constants to handle thread-specific IF, IOPL values */
+			enum {
+				CORE_PD_ID    = 1,
+				EFLAGS_IF_SET = 1 << 9,
+				EFLAGS_IOPL_3 = 3 << 12,
+			};
+
 			/**
 			 * Initialize thread context
 			 *
@@ -287,6 +294,16 @@ class Genode::Cpu
 				translation_table(table);
 
 				Gdt::load(Cpu::exception_entry);
+
+				/*
+				 * Enable interrupts for all threads, set I/O privilege level
+				 * (IOPL) to 3 for core threads to allow UART access.
+				 */
+				eflags = EFLAGS_IF_SET;
+				if (pd_id == CORE_PD_ID)
+				{
+					eflags |= EFLAGS_IOPL_3;
+				}
 			}
 		};
 
diff --git a/repos/base-hw/src/core/spec/x86_64/mode_transition.s b/repos/base-hw/src/core/spec/x86_64/mode_transition.s
index 533b7dec1..946b7ed37 100644
--- a/repos/base-hw/src/core/spec/x86_64/mode_transition.s
+++ b/repos/base-hw/src/core/spec/x86_64/mode_transition.s
@@ -203,9 +203,6 @@
 	mov $_mt_buffer+BUFFER_SIZE, %rsp
 	pushq $0x23
 	pushq SP_OFFSET(%rax)
-
-	/* Set I/O privilege level to 3 and enable interrupts */
-	orq $0x3200, FLAGS_OFFSET(%rax)
 	pushq FLAGS_OFFSET(%rax)
 
 	pushq $0x1b