diff --git a/repos/base-hw/src/bootstrap/spec/arm/cpu.cc b/repos/base-hw/src/bootstrap/spec/arm/cpu.cc index 6ceba7197..1e279c1d4 100644 --- a/repos/base-hw/src/bootstrap/spec/arm/cpu.cc +++ b/repos/base-hw/src/bootstrap/spec/arm/cpu.cc @@ -26,13 +26,7 @@ void Board::Cpu::enable_mmu_and_caches(Genode::addr_t table) Ttbcr::write(1); - Ttbr::access_t ttbr = Ttbr::Ba::masked(table); - Ttbr::Rgn::set(ttbr, Ttbr::CACHEABLE); - if (Mpidr::Me::get(Mpidr::read())) { /* check for SMP system */ - Ttbr::Irgn::set(ttbr, Ttbr::CACHEABLE); - Ttbr::S::set(ttbr, 1); - } else - Ttbr::C::set(ttbr, 1); + Ttbr::access_t ttbr = Ttbr::init(table); Ttbr0::write(ttbr); Ttbr1::write(ttbr); diff --git a/repos/base-hw/src/bootstrap/spec/rpi/platform.cc b/repos/base-hw/src/bootstrap/spec/rpi/platform.cc index 0c3a5be9d..85bd49b5f 100644 --- a/repos/base-hw/src/bootstrap/spec/rpi/platform.cc +++ b/repos/base-hw/src/bootstrap/spec/rpi/platform.cc @@ -78,9 +78,7 @@ unsigned Bootstrap::Platform::enable_mmu() Cpu::Ttbcr::write(1); Genode::addr_t table = (Genode::addr_t)core_pd->table_base; - Cpu::Ttbr::access_t ttbr = Cpu::Ttbr::Ba::masked(table); - Cpu::Ttbr::Rgn::set(ttbr, Cpu::Ttbr::CACHEABLE); - Cpu::Ttbr::C::set(ttbr, 1); + Cpu::Ttbr::access_t ttbr = Cpu::Ttbr::init(table); Cpu::Ttbr0::write(ttbr); Cpu::Ttbr1::write(ttbr); diff --git a/repos/base-hw/src/core/spec/arm/cpu.cc b/repos/base-hw/src/core/spec/arm/cpu.cc index d27e2eb30..58968ea5d 100644 --- a/repos/base-hw/src/core/spec/arm/cpu.cc +++ b/repos/base-hw/src/core/spec/arm/cpu.cc @@ -41,7 +41,7 @@ static Asid_allocator &alloc() { Arm_cpu::Mmu_context::Mmu_context(addr_t table) -: cidr((uint8_t)alloc().alloc()), ttbr0(Ttbr0::init(table)) { } +: cidr((uint8_t)alloc().alloc()), ttbr0(Ttbr::init(table)) { } Genode::Arm_cpu::Mmu_context::~Mmu_context() diff --git a/repos/base-hw/src/core/spec/arm/cpu_support.h b/repos/base-hw/src/core/spec/arm/cpu_support.h index 3b74dca51..18a55e7da 100644 --- a/repos/base-hw/src/core/spec/arm/cpu_support.h +++ b/repos/base-hw/src/core/spec/arm/cpu_support.h @@ -37,27 +37,6 @@ namespace Genode { struct Genode::Arm_cpu : public Hw::Arm_cpu { - /** - * Translation table base register 0 - */ - struct Ttbr0 : Hw::Arm_cpu::Ttbr0 - { - /** - * Return initialized value - * - * \param table base of targeted translation table - */ - static access_t init(addr_t const table) - { - access_t v = Ttbr::Ba::masked((addr_t)table); - Ttbr::Rgn::set(v, Ttbr::CACHEABLE); - Ttbr::S::set(v, Board::SMP ? 1 : 0); - if (Board::SMP) Ttbr::Irgn::set(v, Ttbr::CACHEABLE); - else Ttbr::C::set(v, 1); - return v; - } - }; - struct Fpu_context { uint32_t fpscr { 1UL << 24 }; /* VFP/SIMD - status/control register */ diff --git a/repos/base-hw/src/core/spec/arndale/board.h b/repos/base-hw/src/core/spec/arndale/board.h index ad6414ad9..493b18870 100644 --- a/repos/base-hw/src/core/spec/arndale/board.h +++ b/repos/base-hw/src/core/spec/arndale/board.h @@ -21,8 +21,6 @@ namespace Board { using namespace Hw::Arndale_board; using Pic = Hw::Gicv2; - - static constexpr bool SMP = true; } #endif /* _CORE__SPEC__ARNDALE__BOARD_H_ */ diff --git a/repos/base-hw/src/core/spec/imx53_qsb/board.h b/repos/base-hw/src/core/spec/imx53_qsb/board.h index d14d72ee7..959012a26 100644 --- a/repos/base-hw/src/core/spec/imx53_qsb/board.h +++ b/repos/base-hw/src/core/spec/imx53_qsb/board.h @@ -21,7 +21,6 @@ namespace Board { using namespace Hw::Imx53_qsb_board; using Hw::Pic; - static constexpr bool SMP = false; } #endif /* _CORE__SPEC__IMX53_QSB__BOARD_H_ */ diff --git a/repos/base-hw/src/core/spec/imx6q_sabrelite/board.h b/repos/base-hw/src/core/spec/imx6q_sabrelite/board.h index 5920360d9..db74c2af8 100644 --- a/repos/base-hw/src/core/spec/imx6q_sabrelite/board.h +++ b/repos/base-hw/src/core/spec/imx6q_sabrelite/board.h @@ -24,8 +24,6 @@ namespace Board { using Pic = Hw::Gicv2; using L2_cache = Hw::Pl310; - static constexpr bool SMP = true; - L2_cache & l2_cache(); } diff --git a/repos/base-hw/src/core/spec/imx7d_sabre/board.h b/repos/base-hw/src/core/spec/imx7d_sabre/board.h index 6a3863235..f1c43d565 100644 --- a/repos/base-hw/src/core/spec/imx7d_sabre/board.h +++ b/repos/base-hw/src/core/spec/imx7d_sabre/board.h @@ -21,8 +21,6 @@ namespace Board { using namespace Hw::Imx7d_sabre_board; using Pic = Hw::Gicv2; - - static constexpr bool SMP = true; } #endif /* _CORE__SPEC__IMX7_SABRELITE__BOARD_H_ */ diff --git a/repos/base-hw/src/core/spec/nit6_solox/board.h b/repos/base-hw/src/core/spec/nit6_solox/board.h index 95ac42f87..b230b534f 100644 --- a/repos/base-hw/src/core/spec/nit6_solox/board.h +++ b/repos/base-hw/src/core/spec/nit6_solox/board.h @@ -23,8 +23,6 @@ namespace Board { using Pic = Hw::Gicv2; using L2_cache = Hw::Pl310; - static constexpr bool SMP = true; - L2_cache & l2_cache(); } diff --git a/repos/base-hw/src/core/spec/odroid_xu/board.h b/repos/base-hw/src/core/spec/odroid_xu/board.h index a57370e3e..0308f6a54 100644 --- a/repos/base-hw/src/core/spec/odroid_xu/board.h +++ b/repos/base-hw/src/core/spec/odroid_xu/board.h @@ -21,8 +21,6 @@ namespace Board { using namespace Hw::Odroid_xu_board; using Pic = Hw::Gicv2; - - static constexpr bool SMP = true; } #endif /* _CORE__SPEC__ODROID_XU__BOARD_H_ */ diff --git a/repos/base-hw/src/core/spec/panda/board.h b/repos/base-hw/src/core/spec/panda/board.h index 8a503aa3c..8b91ea0f1 100644 --- a/repos/base-hw/src/core/spec/panda/board.h +++ b/repos/base-hw/src/core/spec/panda/board.h @@ -23,8 +23,6 @@ namespace Board { using Pic = Hw::Gicv2; - static constexpr bool SMP = true; - class L2_cache : public Hw::Pl310 { private: diff --git a/repos/base-hw/src/core/spec/pbxa9/board.h b/repos/base-hw/src/core/spec/pbxa9/board.h index b9905914d..fbdb98252 100644 --- a/repos/base-hw/src/core/spec/pbxa9/board.h +++ b/repos/base-hw/src/core/spec/pbxa9/board.h @@ -22,8 +22,6 @@ namespace Board { using Pic = Hw::Gicv2; - static constexpr bool SMP = true; - L2_cache & l2_cache(); } diff --git a/repos/base-hw/src/core/spec/rpi/board.h b/repos/base-hw/src/core/spec/rpi/board.h index 55635bb63..2d0e15028 100644 --- a/repos/base-hw/src/core/spec/rpi/board.h +++ b/repos/base-hw/src/core/spec/rpi/board.h @@ -20,8 +20,6 @@ namespace Board { using namespace Hw::Rpi_board; - - static constexpr bool SMP = false; }; #endif /* _CORE__SPEC__RPI__BOARD_H_ */ diff --git a/repos/base-hw/src/core/spec/rpi3/board.h b/repos/base-hw/src/core/spec/rpi3/board.h index f60c347cb..05fb0c077 100644 --- a/repos/base-hw/src/core/spec/rpi3/board.h +++ b/repos/base-hw/src/core/spec/rpi3/board.h @@ -19,8 +19,6 @@ namespace Board { using namespace Hw::Rpi3_board; - - static constexpr bool SMP = true; }; #endif /* _CORE__SPEC__RPI3__BOARD_H_ */ diff --git a/repos/base-hw/src/core/spec/usb_armory/board.h b/repos/base-hw/src/core/spec/usb_armory/board.h index 66946154d..abcde3435 100644 --- a/repos/base-hw/src/core/spec/usb_armory/board.h +++ b/repos/base-hw/src/core/spec/usb_armory/board.h @@ -20,10 +20,7 @@ namespace Board { using namespace Hw::Usb_armory_board; - using Hw::Pic; - - static constexpr bool SMP = false; } #endif /* _CORE__SPEC__USB_ARMORY__BOARD_H_ */ diff --git a/repos/base-hw/src/core/spec/wand_quad/board.h b/repos/base-hw/src/core/spec/wand_quad/board.h index 4957a9b2d..ece9b95fa 100644 --- a/repos/base-hw/src/core/spec/wand_quad/board.h +++ b/repos/base-hw/src/core/spec/wand_quad/board.h @@ -24,8 +24,6 @@ namespace Board { using L2_cache = Hw::Pl310; using Pic = Hw::Gicv2; - static constexpr bool SMP = true; - L2_cache & l2_cache(); } diff --git a/repos/base-hw/src/core/spec/zynq_qemu/board.h b/repos/base-hw/src/core/spec/zynq_qemu/board.h index b61c351bb..94835e8af 100644 --- a/repos/base-hw/src/core/spec/zynq_qemu/board.h +++ b/repos/base-hw/src/core/spec/zynq_qemu/board.h @@ -24,8 +24,6 @@ namespace Board { using Pic = Hw::Gicv2; - static constexpr bool SMP = true; - L2_cache & l2_cache(); } diff --git a/repos/base-hw/src/include/hw/spec/arm/cpu.h b/repos/base-hw/src/include/hw/spec/arm/cpu.h index 77b447499..493a8cb7f 100644 --- a/repos/base-hw/src/include/hw/spec/arm/cpu.h +++ b/repos/base-hw/src/include/hw/spec/arm/cpu.h @@ -107,6 +107,18 @@ struct Hw::Arm_cpu struct Irgn_1 : Bitfield<0,1> { }; struct Irgn_0 : Bitfield<6,1> { }; struct Irgn : Genode::Bitset_2 { }; /* inner cache mode */ + + static access_t init(Genode::addr_t table) + { + access_t v = Ttbr::Ba::masked(table); + Ttbr::Rgn::set(v, Ttbr::CACHEABLE); + if (Mpidr::Me::get(Mpidr::read())) { /* check for SMP system */ + Ttbr::Irgn::set(v, Ttbr::CACHEABLE); + Ttbr::S::set(v, 1); + } else + Ttbr::C::set(v, 1); + return v; + }; }; struct Ttbr_64bit : Genode::Register<64>