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hw: add board support for Nitrogen6 SoloX

This commit is contained in:
Stefan Kalkowski 2017-10-19 10:39:11 +02:00 committed by Christian Helmuth
parent 7ffc480db8
commit 55b0dff795
11 changed files with 414 additions and 1 deletions
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14
repos/base-hw/lib/mk/spec/nit6_solox/bootstrap-hw.mk Normal file
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INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/nit6_solox
SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc
SRC_CC += bootstrap/spec/arm/imx6_platform.cc
SRC_CC += hw/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc
NR_OF_CPUS = 1
include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc

18
repos/base-hw/lib/mk/spec/nit6_solox/core-hw.mk Normal file
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#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \author Josef Söntgen
# \author Martin Stein
# \date 2014-02-25
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/nit6_solox
# add C++ sources
SRC_CC += platform_services.cc
NR_OF_CPUS = 1
# include less specific configuration
include $(REP_DIR)/lib/mk/spec/cortex_a9/core-hw.inc

5
repos/base-hw/recipes/src/base-hw-nit6_solox/content.mk Normal file
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include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc
content: enable_board_spec
enable_board_spec: etc/specs.conf
echo "SPECS += nit6_solox" >> etc/specs.conf

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repos/base-hw/recipes/src/base-hw-nit6_solox/hash Normal file
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2019-02-19 931711920aa8f5dd76298326471ebc8da3b551a1

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repos/base-hw/recipes/src/base-hw-nit6_solox/used_apis Normal file
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base-hw
base

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repos/base-hw/src/bootstrap/spec/nit6_solox/board.h Normal file
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/*
* \brief Nit6 SOLOX specific board definitions
* \author Stefan Kalkowski
* \date 2017-10-18
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__BOOTSTRAP__SPEC__NIT6_SOLOX__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__NIT6_SOLOX__BOARD_H_
#include <drivers/defs/nit6_solox.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <spec/arm/cortex_a9_actlr.h>
#include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Board {
using namespace Nit6_solox;
struct L2_cache;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_SIZE = UART_1_MMIO_SIZE,
UART_CLOCK = 0, /* dummy value, not used */
};
static volatile unsigned long initial_values[][2] {
// (IOMUX Controller)
{ 0x20E006C, 0x0},
{ 0x20E00CC, 0x10},
{ 0x20E00D0, 0x10},
{ 0x20E00D4, 0x10},
{ 0x20E00D8, 0x10},
{ 0x20E00DC, 0x10},
{ 0x20E00E0, 0x10},
{ 0x20E00E4, 0x10},
{ 0x20E00E8, 0x10},
{ 0x20E00EC, 0x10},
{ 0x20E00F0, 0x10},
{ 0x20E00F4, 0x10},
{ 0x20E00F8, 0x10},
{ 0x20E00FC, 0x10},
{ 0x20E0100, 0x10},
{ 0x20E0104, 0x10},
{ 0x20E0108, 0x10},
{ 0x20E010C, 0x10},
{ 0x20E0110, 0x10},
{ 0x20E0114, 0x10},
{ 0x20E0118, 0x10},
{ 0x20E011C, 0x10},
{ 0x20E0120, 0x10},
{ 0x20E0124, 0x10},
{ 0x20E0128, 0x10},
{ 0x20E012C, 0x10},
{ 0x20E0130, 0x10},
{ 0x20E0134, 0x10},
{ 0x20E0138, 0x15},
{ 0x20E013C, 0x10},
{ 0x20E0150, 0x5},
{ 0x20E0154, 0x5},
{ 0x20E0158, 0x5},
{ 0x20E0224, 0x5},
{ 0x20E0268, 0x5},
{ 0x20E026C, 0x5},
{ 0x20E0270, 0x3},
{ 0x20E0274, 0x3},
{ 0x20E035C, 0x1b8b1},
{ 0x20E0360, 0x1b8b1},
{ 0x20E0364, 0x1b8b1},
{ 0x20E0368, 0x1b8b1},
{ 0x20E0380, 0x1b0b0},
{ 0x20E0384, 0x170b1},
{ 0x20E0390, 0x110b0},
{ 0x20E0394, 0x110b0},
{ 0x20E0398, 0x110b0},
{ 0x20E039C, 0x110b0},
{ 0x20E03A0, 0x110b0},
{ 0x20E03A4, 0x110b0},
{ 0x20E03A8, 0x110b0},
{ 0x20E03AC, 0x110b0},
{ 0x20E03B0, 0x110b0},
{ 0x20E03B4, 0x110b0},
{ 0x20E03B8, 0x110b0},
{ 0x20E03BC, 0x110b0},
{ 0x20E03C0, 0x110b0},
{ 0x20E03D4, 0xb0b0},
{ 0x20E03D8, 0xb0b0},
{ 0x20E03DC, 0xb0b0},
{ 0x20E03E0, 0xb0b0},
{ 0x20E03E4, 0xb0b0},
{ 0x20E03E8, 0xb0b0},
{ 0x20E03FC, 0x1b8b1},
{ 0x20E0404, 0xb0b1},
{ 0x20E0408, 0x1b0b0},
{ 0x20E0410, 0x1b8b1},
{ 0x20E0414, 0x1b0b0},
{ 0x20E0418, 0x1b0b0},
{ 0x20E041C, 0x1b0b0},
{ 0x20E0420, 0x1b0b0},
{ 0x20E0424, 0x1b0b0},
{ 0x20E0428, 0x1b0b0},
{ 0x20E042C, 0x1b0b0},
{ 0x20E0430, 0x1b0b0},
{ 0x20E0434, 0x1b0b0},
{ 0x20E0438, 0x1b0b0},
{ 0x20E043C, 0x1b0b0},
{ 0x20E0440, 0x1b0b0},
{ 0x20E0444, 0x1b0b0},
{ 0x20E0448, 0x1b0b0},
{ 0x20E044C, 0x1b0b0},
{ 0x20E0450, 0x1b0b0},
{ 0x20E0454, 0x1b0b0},
{ 0x20E0458, 0x1b0b0},
{ 0x20E045C, 0x1b0b0},
{ 0x20E0460, 0x1b0b0},
{ 0x20E0464, 0x1b0b0},
{ 0x20E0468, 0x1b0b0},
{ 0x20E046C, 0x1b0b0},
{ 0x20E0470, 0x1b0b0},
{ 0x20E0474, 0x1b0b0},
{ 0x20E0478, 0x1b0b0},
{ 0x20E047C, 0x1b0b0},
{ 0x20E0480, 0x1b0b0},
{ 0x20E0484, 0x1b0b0},
{ 0x20E0488, 0xb0b0},
{ 0x20E0490, 0x30b0},
{ 0x20E0498, 0x30b1},
{ 0x20E049C, 0x30b0},
{ 0x20E04A0, 0x30b1},
{ 0x20E04A4, 0xb0b1},
{ 0x20E04AC, 0x30b0},
{ 0x20E04B0, 0x30b0},
{ 0x20E04B4, 0x30b0},
{ 0x20E04E0, 0xb0b0},
{ 0x20E04E8, 0xb0b0},
{ 0x20E04F0, 0xb0b0},
{ 0x20E04F4, 0xb0b0},
{ 0x20E0508, 0x3081},
{ 0x20E050C, 0x3081},
{ 0x20E0510, 0x3081},
{ 0x20E0514, 0x3081},
{ 0x20E0518, 0x3081},
{ 0x20E051C, 0x3081},
{ 0x20E0520, 0x30b1},
{ 0x20E0524, 0x30b1},
{ 0x20E0528, 0x30b1},
{ 0x20E052C, 0x30b1},
{ 0x20E0530, 0x30b1},
{ 0x20E0534, 0x30b1},
{ 0x20E0538, 0x3081},
{ 0x20E053C, 0x3081},
{ 0x20E0540, 0x3081},
{ 0x20E0544, 0x3081},
{ 0x20E0548, 0x3081},
{ 0x20E054C, 0x3081},
{ 0x20E0550, 0x30b1},
{ 0x20E0554, 0x30b1},
{ 0x20E0558, 0x30b1},
{ 0x20E055C, 0x30b1},
{ 0x20E0560, 0x30b1},
{ 0x20E0564, 0x30b1},
{ 0x20E056C, 0x30b0},
{ 0x20E0570, 0x1b0b0},
{ 0x20E0574, 0x1b0b0},
{ 0x20E0578, 0x1b0b0},
{ 0x20E057C, 0x1b0b0},
{ 0x20E0598, 0x10071},
{ 0x20E059C, 0x17071},
{ 0x20E05A0, 0x17071},
{ 0x20E05A4, 0x17071},
{ 0x20E05A8, 0x17071},
{ 0x20E05AC, 0x17071},
{ 0x20E05B0, 0x1b0b0},
{ 0x20E05B4, 0x1b0b0},
{ 0x20E05B8, 0x1b0b1},
{ 0x20E05BC, 0x1b0b1},
{ 0x20E05C0, 0x100f9},
{ 0x20E05C4, 0x170f9},
{ 0x20E05C8, 0x170f9},
{ 0x20E05CC, 0x170f9},
{ 0x20E05D0, 0x170f9},
{ 0x20E05D4, 0x170f9},
{ 0x20E05D8, 0x170f9},
{ 0x20E05DC, 0x170f9},
{ 0x20E05E0, 0x170f9},
{ 0x20E05E4, 0x170f9},
{ 0x20E05E8, 0x17071},
{ 0x20E083C, 0x2},
// (Global Power Controller}
{ 0x20DC000, 0x140000},
{ 0x20DC008, 0x2077fe0b},
{ 0x20DC00C, 0xff7db18f},
{ 0x20DC010, 0xfbfe0003},
{ 0x20DC014, 0xff2ff93f},
// (Power Management Unit}
{ 0x20C8120, 0x11775},
{ 0x20C8140, 0x4c0016},
{ 0x20C8160, 0x8003000a},
// (Clock Controller Module}
{ 0x20C4004, 0x20000},
{ 0x20C4018, 0x269114},
{ 0x20C401C, 0x4510a9c0},
{ 0x20C4020, 0x13212c06},
{ 0x20C4028, 0x0},
{ 0x20C402C, 0x4b600},
{ 0x20C4030, 0x30074792},
{ 0x20C4038, 0x12153},
{ 0x20C4054, 0x78},
{ 0x20C4060, 0x10e008e},
{ 0x20C4064, 0x2fe62},
{ 0x20C4068, 0xf0c03f0f},
{ 0x20C406C, 0x333c0c00},
{ 0x20C4070, 0x3fff003f},
{ 0x20C4074, 0xfff33ff3},
{ 0x20C4078, 0xc0c3fc},
{ 0x20C407C, 0xf030fff},
{ 0x20C4080, 0x3cfc33},
{ 0x20C8000, 0x80002053},
{ 0x20C8010, 0x80003040},
{ 0x20C8020, 0x3840},
{ 0x20C8070, 0x119006},
{ 0x20C80A0, 0x80002025},
{ 0x20C80B0, 0x13a74},
{ 0x20C80C0, 0xf4240},
{ 0x20C80E0, 0x8030200f},
{ 0x20C80F0, 0xd3d1d0cc},
{ 0x20C8100, 0x5258d0db}
};
}
struct Board::L2_cache : Hw::Pl310
{
L2_cache(Genode::addr_t mmio) : Hw::Pl310(mmio)
{
Aux::access_t aux = 0;
Aux::Full_line_of_zero::set(aux, true);
Aux::Associativity::set(aux, Aux::Associativity::WAY_16);
Aux::Way_size::set(aux, Aux::Way_size::KB_16);
Aux::Replacement_policy::set(aux, Aux::Replacement_policy::PRAND);
Aux::Ns_lockdown::set(aux, true);
Aux::Data_prefetch::set(aux, true);
Aux::Inst_prefetch::set(aux, true);
Aux::Early_bresp::set(aux, true);
write<Aux>(aux);
Tag_ram::access_t tag_ram = 0;
Tag_ram::Setup_latency::set(tag_ram, 2);
Tag_ram::Read_latency::set(tag_ram, 3);
Tag_ram::Write_latency::set(tag_ram, 1);
write<Tag_ram>(tag_ram);
Data_ram::access_t data_ram = 0;
Data_ram::Setup_latency::set(data_ram, 2);
Data_ram::Read_latency::set(data_ram, 3);
Data_ram::Write_latency::set(data_ram, 1);
write<Data_ram>(data_ram);
Prefetch_ctrl::access_t prefetch = read<Prefetch_ctrl>();
Prefetch_ctrl::Data_prefetch::set(prefetch, 1);
Prefetch_ctrl::Inst_prefetch::set(prefetch, 1);
write<Prefetch_ctrl>(prefetch | 0xF);
}
using Hw::Pl310::invalidate;
void enable()
{
Pl310::mask_interrupts();
write<Control::Enable>(1);
}
void disable() {
write<Control::Enable>(0);
}
};
#endif /* _SRC__BOOTSTRAP__SPEC__NIT6_SOLOX__BOARD_H_ */

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repos/base-hw/src/core/spec/nit6_solox/board.h Normal file
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/*
* \brief Board driver
* \author Stefan Kalkowski
* \date 2017-10-18
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__NIT6_SOLOX__BOARD_H_
#define _CORE__SPEC__NIT6_SOLOX__BOARD_H_
/* base includes */
#include <drivers/defs/nit6_solox.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Board {
using namespace Nit6_solox;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using L2_cache = Hw::Pl310;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* dummy value, not used */
};
static constexpr bool SMP = true;
L2_cache & l2_cache();
}
#endif /* _CORE__SPEC__NIT6_SOLOX__BOARD_H_ */

31
repos/base/include/drivers/defs/nit6_solox.h Normal file
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/*
* \brief MMIO and IRQ definitions for Nit6 SOLOX board
* \author Stefan Kalkowski
* \date 2017-10-18
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__DEFS__NIT6_SOLOX_H_
#define _INCLUDE__DRIVERS__DEFS__NIT6_SOLOX_H_
/* Genode includes */
#include <drivers/defs/imx6.h>
namespace Nit6_solox {
using namespace Imx6;
enum {
/* normal RAM */
RAM_BASE = 0x80000000,
RAM_SIZE = 0x40000000,
};
};
#endif /* _INCLUDE__DRIVERS__DEFS__NIT6_SOLOX_H_ */

5
repos/base/mk/spec/nit6_solox.mk Normal file
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@ -0,0 +1,5 @@
SPECS += imx6
REP_INC_DIR += include/spec/nit6_solox
include $(BASE_DIR)/mk/spec/imx6.mk

4
tool/create_builddir
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@ -12,7 +12,7 @@ PLATFORM = $(MAKECMDGOALS)
PLATFORMS = x86_32 x86_64 panda pbxa9 rpi arndale imx53_qsb imx53_qsb_tz \
usb_armory wand_quad odroid_xu odroid_x2 zynq_qemu muen \
imx6q_sabrelite riscv_spike linux
imx6q_sabrelite riscv_spike linux nit6_solox
PLATFORMS_DEPR = linux_x86 linux_arm fiasco_x86 okl4_x86 pistachio_x86 \
nova_x86_32 nova_x86_64 hw_x86_64 foc_x86_32 foc_x86_64 \
@ -150,6 +150,7 @@ BUILD_CONF(zynq_qemu) := run_kernel_hw run_qemu run_opt_hw run_boot_dir qemu_
BUILD_CONF(muen) := run_kernel_hw run_opt_muen run_boot_dir repos repos_x86
BUILD_CONF(riscv_spike) := run_kernel_hw run_opt_spike run_boot_dir repos
BUILD_CONF(linux) := run_kernel_linux repos
BUILD_CONF(nit6_solox) := run_kernel_hw run_boot_dir repos
# deprecated platforms, to be removed
BUILD_CONF(linux_x86) := run_kernel_linux repos
@ -234,6 +235,7 @@ SPECS(zynq_qemu) := zynq_qemu
SPECS(muen) := muen x86_64
SPECS(riscv_spike) := riscv
SPECS(linux) := $(HOST_SPEC_ARCH)
SPECS(nit6_solox) := nit6_solox
# deprecated platforms
SPECS(linux_x86) := $(HOST_SPEC_ARCH)

2
tool/run/boot_dir/hw
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@ -18,6 +18,7 @@ proc bootstrap_link_address { } {
if {[have_spec "zynq"]} { return "0x00100000" }
if {[have_spec "riscv"]} { return "0x81000000" }
if {[have_spec "rpi"]} { return "0x00800000" }
if {[have_spec "nit6_solox"]} { return "0x88000000" }
puts "unknown platform no linker address known"
exit -1
@ -211,6 +212,7 @@ proc base_src { } {
if {[have_spec pbxa9]} { return base-hw-pbxa9 }
if {[have_spec rpi]} { return base-hw-rpi }
if {[have_spec imx6q_sabrelite]} { return base-hw-imx6q_sabrelite }
if {[have_spec nit6_solox]} { return base-hw-nit6_solox }
if {[have_spec odroid_xu]} { return base-hw-odroid_xu }
if {[have_spec imx53_qsb] && ![have_spec trustzone]} { return base-hw-imx53_qsb }
if {[have_spec imx53_qsb] && [have_spec trustzone]} { return base-hw-imx53_qsb_tz }