hw_vea9x4: quickfix slow RAM access
Setting the ACTLR.SMP bit also without SMP support fastens RAM access significantly. A proper solution would implement SMP support which must enable the bit anyway. Fixes #1353
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467eee07a6
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@ -13,6 +13,7 @@ INC_DIR += $(REP_DIR)/src/core/include/spec/pl011
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# add C++ sources
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# add C++ sources
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SRC_CC += platform_services.cc
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SRC_CC += platform_services.cc
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SRC_CC += spec/vea9x4/platform_support.cc
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SRC_CC += spec/vea9x4/platform_support.cc
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SRC_CC += spec/vea9x4/board.cc
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SRC_CC += spec/cortex_a9/pic.cc
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SRC_CC += spec/cortex_a9/pic.cc
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SRC_CC += spec/arm_gic/pic.cc
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SRC_CC += spec/arm_gic/pic.cc
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@ -213,6 +213,24 @@ class Genode::Cpu : public Arm_v7
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public:
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public:
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/**
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* Auxiliary Control Register
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*/
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struct Actlr : Register<32>
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{
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struct Smp : Bitfield<6, 1> { };
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static access_t read()
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{
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access_t v;
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asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (v) :: );
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return v;
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}
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static void write(access_t const v) {
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asm volatile ("mcr p15, 0, %0, c1, c0, 1" :: "r" (v) : ); }
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};
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enum
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enum
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{
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{
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/* interrupt controller */
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/* interrupt controller */
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@ -25,7 +25,7 @@ namespace Genode
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static void outer_cache_invalidate() { }
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static void outer_cache_invalidate() { }
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static void outer_cache_flush() { }
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static void outer_cache_flush() { }
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static void prepare_kernel() { }
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static void prepare_kernel();
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static void secondary_cpus_ip(void * const ip) { }
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static void secondary_cpus_ip(void * const ip) { }
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/**
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/**
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29
repos/base-hw/src/core/spec/vea9x4/board.cc
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29
repos/base-hw/src/core/spec/vea9x4/board.cc
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@ -0,0 +1,29 @@
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/*
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* \brief Board driver for core
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* \author Martin Stein
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* \date 2015-02-16
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*/
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/*
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* Copyright (C) 2012-2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* core includes */
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#include <cpu.h>
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using namespace Genode;
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void Board::prepare_kernel()
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{
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/**
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* FIXME We enable this bit although base-hw doesn't support
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* SMP because it fastens RAM access significantly.
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*/
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Cpu::Actlr::access_t actlr = Cpu::Actlr::read();
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Cpu::Actlr::Smp::set(actlr, 1);
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Cpu::Actlr::write(actlr);
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}
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