From 2eccfc5dc9c88766ef36a79e045ddfa5717f806f Mon Sep 17 00:00:00 2001 From: Martin Stein Date: Thu, 24 May 2012 12:52:45 +0200 Subject: [PATCH] Defs for the boards, supported by 'base-hw' --- base/include/drivers/board/panda_a2.h | 53 ++++++++++++++++++ base/include/drivers/board/pbxa9.h | 78 +++++++++++++++++++++++++++ base/include/drivers/board/vea9x4.h | 64 ++++++++++++++++++++++ 3 files changed, 195 insertions(+) create mode 100644 base/include/drivers/board/panda_a2.h create mode 100644 base/include/drivers/board/pbxa9.h create mode 100644 base/include/drivers/board/vea9x4.h diff --git a/base/include/drivers/board/panda_a2.h b/base/include/drivers/board/panda_a2.h new file mode 100644 index 000000000..5cc0de8ac --- /dev/null +++ b/base/include/drivers/board/panda_a2.h @@ -0,0 +1,53 @@ +/** + * \brief Driver for the OMAP4 PandaBoard revision A2 + * \author Martin stein + * \date 2011-11-03 + */ + +/* + * Copyright (C) 2011-2012 Genode Labs GmbH + * + * This file is part of the Genode OS framework, which is distributed + * under the terms of the GNU General Public License version 2. + */ + +#ifndef _BASE__INCLUDE__DRIVERS__BOARD__PANDA_A2_H_ +#define _BASE__INCLUDE__DRIVERS__BOARD__PANDA_A2_H_ + +namespace Genode +{ + /** + * Driver for the OMAP4 PandaBoard revision A2 + */ + struct Panda_a2 + { + enum + { + /* Buses */ + L4_PER_BASE = 0x48000000, + L4_PER_SIZE = 0x01000000, + + /* Clocks */ + MPU_DPLL_CLOCK = 200*1000*1000, + + /* UART */ + TL16C750_3_MMIO_BASE = L4_PER_BASE + 0x20000, + TL16C750_3_MMIO_SIZE = 0x2000, + TL16C750_3_CLOCK = 48*1000*1000, + TL16C750_3_IRQ = 74, + + /* CPU */ + CORTEX_A9_PRIVATE_MEM_BASE = L4_PER_BASE + 0x240000, + CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000, + CORTEX_A9_CLOCK = MPU_DPLL_CLOCK, + CORTEX_A9_SECURITY_EXTENSION = 0, + + /* RAM */ + EMIF1_EMIF2_CS0_SDRAM_BASE = 0x80000000, + EMIF1_EMIF2_CS0_SDRAM_SIZE = 0x40000000, + }; + }; +} + +#endif /* _BASE__INCLUDE__DRIVERS__BOARD__PANDA_A2_H_ */ + diff --git a/base/include/drivers/board/pbxa9.h b/base/include/drivers/board/pbxa9.h new file mode 100644 index 000000000..46f342d2d --- /dev/null +++ b/base/include/drivers/board/pbxa9.h @@ -0,0 +1,78 @@ +/** + * \brief Driver for the Realview PBXA9 board + * \author Martin stein + * \date 2011-11-03 + */ + +/* + * Copyright (C) 2011-2012 Genode Labs GmbH + * + * This file is part of the Genode OS framework, which is distributed + * under the terms of the GNU General Public License version 2. + */ + +#ifndef _BASE__INCLUDE__DRIVERS__BOARD__PBXA9_H_ +#define _BASE__INCLUDE__DRIVERS__BOARD__PBXA9_H_ + +namespace Genode +{ + /** + * Driver for the Realview PBXA9 board + */ + struct Pbxa9 + { + enum + { + /* Northbridge */ + NORTHBRIDGE_DDR_0_BASE = 0x00000000, /* DMC mirror */ + NORTHBRIDGE_DDR_0_SIZE = 256*1024*1024, + + NORTHBRIDGE_AHB_BASE = 0x10020000, + NORTHBRIDGE_AHB_SIZE = 768*1024, + + /* Southbridge */ + SOUTHBRIDGE_APB_BASE = 0x10000000, + SOUTHBRIDGE_APB_SIZE = 128*1024, + + /* Clocks */ + OSC_6_CLOCK = 24*1000*1000, + OSC_7_CLOCK = 14*1000*1000, + + /* CPU */ + CORTEX_A9_CLOCK = OSC_7_CLOCK * 5, + CORTEX_A9_PRIVATE_MEM_BASE = 0x1f000000, + CORTEX_A9_PRIVATE_MEM_SIZE = 0x01000000, + CORTEX_A9_SECURITY_EXTENSION = 0, + + /* UART */ + PL011_0_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x9000, + PL011_0_MMIO_SIZE = 4*1024, + PL011_0_CLOCK = OSC_6_CLOCK, + PL011_0_IRQ = 44, + + /* Timer */ + SP804_0_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x11000, + SP804_0_MMIO_SIZE = 4*1024, + SP804_0_IRQ = 36, + SP804_0_CLOCK = 1*1000*1000, + + SP804_1_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x12000, + SP804_1_MMIO_SIZE = 4*1024, + SP804_1_IRQ = 37, + SP804_1_CLOCK = 1*1000*1000, + + SP804_2_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x18000, + SP804_2_MMIO_SIZE = 4*1024, + SP804_2_IRQ = 73, + SP804_2_CLOCK = 1*1000*1000, + + SP804_3_MMIO_BASE = SOUTHBRIDGE_APB_BASE + 0x19000, + SP804_3_MMIO_SIZE = 4*1024, + SP804_3_IRQ = 74, + SP804_3_CLOCK = 1*1000*1000, + }; + }; +} + +#endif /* _BASE__INCLUDE__DRIVERS__BOARD__PBXA9_H_ */ + diff --git a/base/include/drivers/board/vea9x4.h b/base/include/drivers/board/vea9x4.h new file mode 100644 index 000000000..6260da0b1 --- /dev/null +++ b/base/include/drivers/board/vea9x4.h @@ -0,0 +1,64 @@ +/** + * \brief Driver for the Versatile Express A9X4 board + * \author Martin stein + * \date 2011-11-03 + */ + +/* + * Copyright (C) 2011-2012 Genode Labs GmbH + * + * This file is part of the Genode OS framework, which is distributed + * under the terms of the GNU General Public License version 2. + */ + +#ifndef _BASE__INCLUDE__DRIVERS__BOARD__VEA9X4_H_ +#define _BASE__INCLUDE__DRIVERS__BOARD__VEA9X4_H_ + +namespace Genode +{ + /** + * Driver for the Versatile Express A9X4 board + * + * \detail Implies the uATX motherboard and the + * CoreTile Express A9X4 daughterboard + */ + struct Vea9x4 + { + enum + { + /* Static memory bus */ + SMB_CS7_BASE = 0x10000000, + SMB_CS7_SIZE = 0x20000, + SMB_CS0_TO_CS6_BASE = 0x40000000, + SMB_CS0_TO_CS6_SIZE = 0x20000000, + + /* UART */ + PL011_0_MMIO_BASE = SMB_CS7_BASE + 0x9000, + PL011_0_MMIO_SIZE = 0x1000, + PL011_0_CLOCK = 24*1000*1000, + PL011_0_IRQ = 5, + + /* Timer/counter */ + SP804_0_1_MMIO_BASE = SMB_CS7_BASE + 0x11000, + SP804_0_1_MMIO_SIZE = 0x1000, + SP804_0_1_CLOCK = 1000*1000, + SP804_0_1_IRQ = 34, + + /* Clocks */ + TCREF_CLOCK = 66670*1000, + + /* CPU */ + CORTEX_A9_PRIVATE_MEM_BASE = 0x1e000000, + CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000, + CORTEX_A9_CLOCK = TCREF_CLOCK, + CORTEX_A9_SECURITY_EXTENSION = 1, + + /* RAM */ + LOCAL_DDR2_BASE = 0x60000000, + LOCAL_DDR2_SIZE = 0x40000000, + }; + }; +} + +#endif /* _BASE__INCLUDE__DRIVERS__BOARD__VEA9X4_H_ */ +