Update L4ka::Pistachio, fix gcc-4.7 problem
With the update to L4ka::Pistachio, we no longer need to patch the contrib sources. Our patch went upstream in the meanwhile. Apparently, gcc-4.7 is picky about specifying the '-melf_i386' argument at the command line of the GCC frontend. We need to make sure to use the '-Wl,' prefix.
This commit is contained in:
Norman Feske
parent
05e60691cb
commit
2a03c78dfb
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@ -7,8 +7,9 @@
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VERBOSE = @
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ECHO = @echo
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GIT_URI = https://github.com/l4ka/pistachio.git
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GIT_REV = 5c1b29b9c77fbd4760f35507da3d2f548f4364bd
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GIT_REV = 76bac3d926dc707c6a3243b38c1505d2b5b6537b
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CONTRIB_DIR = contrib
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SHELL = bash
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PATCHES = $(shell find patches -name *.patch)
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#
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@ -54,8 +55,8 @@ prepare: $(CONTRIB_DIR)
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$(VERBOSE)cd $(CONTRIB_DIR); git fetch; git reset --hard $(GIT_REV)
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@# use GCC front end for as linker for the pistachio user land
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$(VERBOSE)sed -i "/LD=/s/^.*$$/LD=\$$(CC)/" $(CONTRIB_DIR)/user/config.mk.in
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$(ECHO) "applying patches to '$(CONTRIB_DIR)/'"
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$(VERBOSE)for i in $(PATCHES); do patch -d $(CONTRIB_DIR) -p1 < $$i; done
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@# add '-Wl,' prefix to '-melf_*' linker options
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$(VERBOSE)sed -i "s/-melf_/-Wl,-melf_/" `grep -rl melf_ $(CONTRIB_DIR)/user`
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$(VERBOSE)for i in cmlcompile.py cmlconfigure.py configtrans.py; do \
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sed -i "s/env python/env $(PYTHON2)/" $(CONTRIB_DIR)/contrib/cml2/$$i; done
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$(VERBOSE)cd $(CONTRIB_DIR)/user; autoheader; autoconf;
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@ -1,20 +0,0 @@
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This directory contains patches for the Pistachio microkernel
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:'syscalls_ia32.patch':
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GCC 4.6 switches from base-pointer-relative addressing to stack-pointer-
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relative addressing for memory-input constraints of inline assembler. Therefore
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the syscall bindings are adapted to these requirements.
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Applying the patches
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--------------------
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To apply a patch to the Pistachio kernel, use the 'patch' command. First check
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the directory given at the header of the patch. It may contain a directory
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prefix (such as 'a/'), which does not actually exist. This prefix is usually
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generated by the tool used to create the patch. In this case, use the '-p'
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option of the patch command. To apply the patch with the first part of the
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path stripped, issue the following command (make sure that you changed to
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the base directory of the Pistachio kernel):
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! patch -p1 < /path/to/utcb.patch
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@ -1,280 +0,0 @@
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diff --git a/user/include/l4/ia32/syscalls.h b/user/include/l4/ia32/syscalls.h
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index 56820e3..2307ed9 100644
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--- a/user/include/l4/ia32/syscalls.h
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+++ b/user/include/l4/ia32/syscalls.h
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@@ -47,6 +47,13 @@
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# define __L4_CLOBBER_REGS "ebx", "cc"
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#endif
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+/*
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+ * This expects the '__L4_indirect' struct in 'edi'
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+ */
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+#define __L4_INDIRECT_CALL " movl 4(%%edi), %%ebx \n" \
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+ " movl (%%edi), %%edi \n" \
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+ " call *%%ebx \n"
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+
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#ifdef __cplusplus
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#define _C_ "C"
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#else
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@@ -70,6 +77,13 @@ extern _C_ void __L4_SpaceControl(void);
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extern _C_ void __L4_ProcessorControl(void);
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extern _C_ void __L4_MemoryControl(void);
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+typedef struct __L4_indirect
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+{
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+ L4_Word_t edi;
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+ void (*sys_call)();
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+} __L4_indirect;
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+
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+
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L4_INLINE void * L4_KernelInterface (L4_Word_t *ApiVersion,
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L4_Word_t *ApiFlags,
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L4_Word_t *KernelId)
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@@ -163,12 +177,14 @@ L4_INLINE L4_Word_t L4_ThreadControl (L4_ThreadId_t dest,
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L4_Word_t result;
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L4_Word_t dummy;
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+ __L4_indirect in;
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+ in.edi = (L4_Word_t)UtcbLocation;
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+ in.sys_call = __L4_ThreadControl;
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+
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__asm__ __volatile__ (
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"/* L4_ThreadControl() */ \n"
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__L4_SAVE_REGS
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- " movl %%edi, %%ebx \n"
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- " movl %9, %%edi \n"
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- " call *%%ebx \n"
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+ __L4_INDIRECT_CALL
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__L4_RESTORE_REGS
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: /* outputs */
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@@ -183,11 +199,10 @@ L4_INLINE L4_Word_t L4_ThreadControl (L4_ThreadId_t dest,
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"1" (Pager),
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"2" (Scheduler),
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"3" (SpaceSpecifier),
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- "m" (UtcbLocation),
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- "D" (__L4_ThreadControl)
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+ "4" (&in)
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: /* clobbers */
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- __L4_CLOBBER_REGS);
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+ __L4_CLOBBER_REGS, "memory");
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return result;
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}
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@@ -239,12 +254,14 @@ L4_INLINE L4_Word_t L4_Schedule (L4_ThreadId_t dest,
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L4_Word_t result;
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L4_Word_t dummy;
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+ __L4_indirect in;
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+ in.edi = PreemptionControl;
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+ in.sys_call = __L4_Schedule;
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+
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__asm__ __volatile__ (
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"/* L4_Schedule() */ \n"
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__L4_SAVE_REGS
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- " movl %%edi, %%ebx \n"
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- " movl %9, %%edi \n"
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- " call *%%ebx \n"
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+ __L4_INDIRECT_CALL
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__L4_RESTORE_REGS
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: /* outputs */
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@@ -259,11 +276,11 @@ L4_INLINE L4_Word_t L4_Schedule (L4_ThreadId_t dest,
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"1" (PrioControl),
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"2" (TimeControl),
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"3" (ProcessorControl),
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- "m" (PreemptionControl),
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- "D" (__L4_Schedule)
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+ "4" (&in)
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: /* clobbers */
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- __L4_CLOBBER_REGS);
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+ __L4_CLOBBER_REGS, "memory");
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+
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return result;
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}
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@@ -278,14 +295,15 @@ L4_INLINE L4_MsgTag_t L4_Ipc (L4_ThreadId_t to,
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L4_Word_t * utcb = __L4_X86_Utcb ();
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#if defined(__pic__)
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+ __L4_indirect in;
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+ in.edi = (L4_Word_t)utcb;
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+ in.sys_call = __L4_Ipc;
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__asm__ __volatile__ (
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"/* L4_Ipc() */ \n"
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__L4_SAVE_REGS
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- " movl %%eax, %%ebx \n"
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- " movl %5, %%eax \n"
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- " call *%%ebx \n"
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- " movl %%ebp, %%ecx \n"
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+ __L4_INDIRECT_CALL
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+ " movl %%ebp, %%ecx \n"
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" movl %%ebx, %%edx \n"
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__L4_RESTORE_REGS
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@@ -297,12 +315,12 @@ L4_INLINE L4_MsgTag_t L4_Ipc (L4_ThreadId_t to,
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: /* inputs */
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"S" (utcb[0]),
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- "m" (to.raw),
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- "D" (utcb),
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+ "a" (to.raw),
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+ "D" (&in),
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"c" (Timeouts),
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- "d" (FromSpecifier),
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- "a" (__L4_Ipc)
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- );
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+ "d" (FromSpecifier)
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+
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+ : "memory");
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#else
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L4_Word_t dummy;
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@@ -319,7 +337,7 @@ L4_INLINE L4_MsgTag_t L4_Ipc (L4_ThreadId_t to,
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"=a" (result),
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"=b" (mr1),
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"=c" (mr2),
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- "=d" (dummy)
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+ "=d" (dummy)
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: /* inputs */
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"S" (utcb[0]),
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@@ -351,12 +369,15 @@ L4_INLINE L4_MsgTag_t L4_Lipc (L4_ThreadId_t to,
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L4_Word_t * utcb = __L4_X86_Utcb ();
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#if defined(__pic__)
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+
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+ __L4_indirect in;
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+ in.edi = (L4_Word_t)utcb;
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+ in.sys_call = __L4_Lipc;
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+
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__asm__ __volatile__ (
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"/* L4_Lipc() */ \n"
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__L4_SAVE_REGS
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- " movl %%eax, %%ebx \n"
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- " movl %5, %%eax \n"
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- " call *%%ebx \n"
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+ __L4_INDIRECT_CALL
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" movl %%ebp, %%ecx \n"
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" movl %%ebx, %%edx \n"
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__L4_RESTORE_REGS
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@@ -366,15 +387,15 @@ L4_INLINE L4_MsgTag_t L4_Lipc (L4_ThreadId_t to,
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"=a" (result),
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"=d" (mr1),
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"=c" (mr2)
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-
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+
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: /* inputs */
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"S" (utcb[0]),
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- "m" (to.raw),
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- "D" (utcb),
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+ "a" (to.raw),
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+ "D" (&in),
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"c" (Timeouts),
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- "d" (FromSpecifier),
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- "a" (__L4_Lipc)
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- );
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+ "d" (FromSpecifier)
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+
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+ : "memory");
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#else
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L4_Word_t dummy;
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@@ -382,7 +403,7 @@ L4_INLINE L4_MsgTag_t L4_Lipc (L4_ThreadId_t to,
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"/* L4_Lipc() */ \n"
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__L4_SAVE_REGS
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" call __L4_Lipc \n"
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- " movl %%ebp, %%ecx \n"
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+ " movl %%ebp, %%ecx \n"
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__L4_RESTORE_REGS
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: /* outputs */
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@@ -390,8 +411,8 @@ L4_INLINE L4_MsgTag_t L4_Lipc (L4_ThreadId_t to,
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"=a" (result),
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"=b" (mr1),
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"=c" (mr2),
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- "=d" (dummy)
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-
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+ "=d" (dummy)
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+
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: /* inputs */
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"S" (utcb[0]),
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"a" (to.raw),
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@@ -446,12 +467,14 @@ L4_INLINE L4_Word_t L4_SpaceControl (L4_ThreadId_t SpaceSpecifier,
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{
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L4_Word_t result, dummy;
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+ __L4_indirect in;
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+ in.edi = redirector.raw;
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+ in.sys_call = __L4_SpaceControl;
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+
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__asm__ __volatile__ (
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"/* L4_SpaceControl() */ \n"
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__L4_SAVE_REGS
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- " movl %%edi, %%ebx \n"
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- " movl %9, %%edi \n"
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- " call *%%ebx \n"
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+ __L4_INDIRECT_CALL
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__L4_RESTORE_REGS
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: /* outputs */
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@@ -466,11 +489,10 @@ L4_INLINE L4_Word_t L4_SpaceControl (L4_ThreadId_t SpaceSpecifier,
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"1" (control),
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"2" (KernelInterfacePageArea),
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"3" (UtcbArea),
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- "m" (redirector),
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- "D" (__L4_SpaceControl)
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+ "4" (&in)
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: /* clobbers */
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- __L4_CLOBBER_REGS);
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+ __L4_CLOBBER_REGS, "memory");
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return result;
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}
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@@ -516,22 +538,23 @@ L4_INLINE L4_Word_t L4_MemoryControl (L4_Word_t control,
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L4_Word_t result, dummy;
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L4_Word_t * utcb = __L4_X86_Utcb ();
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+ __L4_indirect in;
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+ in.edi = (L4_Word_t)utcb;
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+ in.sys_call = __L4_MemoryControl;
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+
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__asm__ __volatile__ (
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"/* L4_MemoryControl() */ \n"
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__L4_SAVE_REGS
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- " pushl %%edi \n"
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- " movl %8, %%edi \n"
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" movl 12(%6), %%ebp \n"
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" movl 8(%6), %%ebx \n"
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" movl 4(%6), %%edx \n"
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" movl (%6), %%ecx \n"
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- " call *(%%esp) \n"
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- " popl %%edi \n"
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+ __L4_INDIRECT_CALL
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__L4_RESTORE_REGS
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: /* outputs */
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"=a" (result),
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- "=c" (dummy),
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+ "=c" (dummy),
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"=d" (dummy),
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"=S" (dummy),
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"=D" (dummy)
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@@ -540,11 +563,10 @@ L4_INLINE L4_Word_t L4_MemoryControl (L4_Word_t control,
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"0" (control),
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"1" (attributes),
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"3" (utcb[0]),
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- "m" (utcb),
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- "4" (__L4_MemoryControl)
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+ "4" (&in)
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: /* clobbers */
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- __L4_CLOBBER_REGS);
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+ __L4_CLOBBER_REGS, "memory");
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return result;
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}
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