From 2278104a8de85f10f2ff86e198e8124e3c7b1d18 Mon Sep 17 00:00:00 2001
From: Hinnerk van Bruinehsen <h.v.bruinehsen@fu-berlin.de>
Date: Fri, 13 Apr 2018 13:44:42 +0200
Subject: [PATCH] sel4: update to version 9.0.0

---
 repos/base-sel4/patches/config.patch          |  8 ++---
 repos/base-sel4/ports/sel4.hash               |  2 +-
 repos/base-sel4/ports/sel4.port               |  4 +--
 .../base-sel4/src/core/include/thread_sel4.h  |  4 +--
 repos/base-sel4/src/core/platform.cc          | 31 +++++++++++++------
 5 files changed, 31 insertions(+), 18 deletions(-)

diff --git a/repos/base-sel4/patches/config.patch b/repos/base-sel4/patches/config.patch
index e26755563..a0dde99cb 100644
--- a/repos/base-sel4/patches/config.patch
+++ b/repos/base-sel4/patches/config.patch
@@ -31,12 +31,12 @@
  #endif
 --- src/kernel/sel4/include/plat/pc99/plat/64/plat_mode/machine/hardware.h
 +++ src/kernel/sel4/include/plat/pc99/plat/64/plat_mode/machine/hardware.h
-@@ -23,7 +23,7 @@
+@@ -19,7 +19,7 @@
   * because they need to defined like this in linker.lds
   */
- #define PADDR_BASE  0x00000000ul
--#define PADDR_LOAD  0x00100000ul
-+#define PADDR_LOAD  0x00200000ul
+ #define PADDR_BASE  UL_CONST(0x00000000)
+-#define PADDR_LOAD  UL_CONST(0x00100000)
++#define PADDR_LOAD  UL_CONST(0x00200000)
  /* our kernel window is 2^39 bits (2^9 * 1gb) and the virtual address
   * range is 48 bits. Therefore our base is 2^48 - 2^39
   */
diff --git a/repos/base-sel4/ports/sel4.hash b/repos/base-sel4/ports/sel4.hash
index e23a243fd..77cf9ba33 100644
--- a/repos/base-sel4/ports/sel4.hash
+++ b/repos/base-sel4/ports/sel4.hash
@@ -1 +1 @@
-f3cba0b8aeccaf78be076894186da3503a7e9fd1
+d006609b01c27aa7f016b2eb8740b1afb3587354
diff --git a/repos/base-sel4/ports/sel4.port b/repos/base-sel4/ports/sel4.port
index d422da96b..6a8005e0c 100644
--- a/repos/base-sel4/ports/sel4.port
+++ b/repos/base-sel4/ports/sel4.port
@@ -3,8 +3,8 @@ VERSION   := git
 DOWNLOADS := sel4.git
 
 URL(sel4) := https://github.com/seL4/seL4.git
-# master branch, version 7.0 + already merged multiboot2 and uefi support
-REV(sel4) := a2d974f47f876bb71950ef3a7cb8f695fa4f7d80
+# master branch, version 9.0
+REV(sel4) := f58d22af8b6ce8bfccaa4bac393a31cad670e7c1
 DIR(sel4) := src/kernel/sel4
 
 $(call check_tool,python)
diff --git a/repos/base-sel4/src/core/include/thread_sel4.h b/repos/base-sel4/src/core/include/thread_sel4.h
index 3497e11e2..341caa0b0 100644
--- a/repos/base-sel4/src/core/include/thread_sel4.h
+++ b/repos/base-sel4/src/core/include/thread_sel4.h
@@ -66,8 +66,8 @@ void Genode::Thread_info::init_tcb(Platform &platform,
 	create<Tcb_kobj>(service, platform.core_cnode().sel(), tcb_sel);
 
 	/* set scheduling priority */
-	seL4_TCB_SetMCPriority(tcb_sel.value(), prio);
-	seL4_TCB_SetPriority(tcb_sel.value(), prio);
+	seL4_TCB_SetMCPriority(tcb_sel.value(), Cnode_index(seL4_CapInitThreadTCB).value(), prio);
+	seL4_TCB_SetPriority(tcb_sel.value(), Cnode_index(seL4_CapInitThreadTCB).value(), prio);
 
 	/* place at cpu */
 	affinity_sel4_thread(tcb_sel, cpu);
diff --git a/repos/base-sel4/src/core/platform.cc b/repos/base-sel4/src/core/platform.cc
index 2172c0dc7..9999fcb60 100644
--- a/repos/base-sel4/src/core/platform.cc
+++ b/repos/base-sel4/src/core/platform.cc
@@ -378,15 +378,6 @@ void Platform::_init_rom_modules()
 	Genode::Xml_generator xml(reinterpret_cast<char *>(virt_addr),
 	                          rom_size, rom_name, [&] ()
 	{
-		xml.node("hardware", [&] () {
-			xml.node("features", [&] () {
-				xml.attribute("svm", false);
-				xml.attribute("vmx", false);
-			});
-			xml.node("tsc", [&] () {
-				xml.attribute("freq_khz" , bi.archInfo * 1000UL);
-			});
-		});
 
 		if (!bi.extraLen)
 			return;
@@ -402,6 +393,28 @@ void Platform::_init_rom_modules()
 		     next <= last && element->id != SEL4_BOOTINFO_HEADER_PADDING;
 			 element = next)
 		{
+			if (element->id == SEL4_BOOTINFO_HEADER_X86_TSC_FREQ) {
+				struct tsc_freq {
+					uint32_t freq_mhz;
+				} __attribute__((packed));
+				if (sizeof(tsc_freq) + sizeof(*element) != element->len) {
+					error("unexpected tsc frequency format");
+					continue;
+				}
+
+				tsc_freq const * boot_freq = reinterpret_cast<tsc_freq const *>(reinterpret_cast<addr_t>(element) + sizeof(* element));
+
+				xml.node("hardware", [&] () {
+					xml.node("features", [&] () {
+						xml.attribute("svm", false);
+						xml.attribute("vmx", false);
+					});
+					xml.node("tsc", [&] () {
+						xml.attribute("freq_khz" , boot_freq->freq_mhz * 1000UL);
+					});
+				});
+			}
+
 			if (element->id == SEL4_BOOTINFO_HEADER_X86_FRAMEBUFFER) {
 				struct mbi2_framebuffer {
 					uint64_t addr;