Stefan Kalkowski
Christian Helmuth
parent
e3f82b09d7
commit
1cbd77c806
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@ -7,6 +7,8 @@ SRC_CC += lib/base/arm_64/kernel/interface.cc
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SRC_CC += spec/64bit/memory_map.cc
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SRC_S += bootstrap/spec/arm_64/crt0.s
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NR_OF_CPUS = 4
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vpath spec/64bit/memory_map.cc $(BASE_DIR)/../base-hw/src/lib/hw
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include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
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@ -2,13 +2,13 @@ INC_DIR += $(REP_DIR)/src/core/spec/imx8q_evk
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INC_DIR += $(REP_DIR)/src/core/spec/arm_v8
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# add C++ sources
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SRC_CC += kernel/cpu_up.cc
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SRC_CC += kernel/lock.cc
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SRC_CC += kernel/cpu_mp.cc
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SRC_CC += kernel/vm_thread_off.cc
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SRC_CC += platform_services.cc
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SRC_CC += spec/64bit/memory_map.cc
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SRC_CC += spec/arm/generic_timer.cc
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SRC_CC += spec/arm/gicv3.cc
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SRC_CC += spec/arm/kernel/lock.cc
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SRC_CC += spec/arm/platform_support.cc
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SRC_CC += spec/arm_v8/cpu.cc
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SRC_CC += spec/arm_v8/kernel/cpu.cc
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@ -20,5 +20,7 @@ SRC_S += spec/arm_v8/crt0.s
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vpath spec/64bit/memory_map.cc $(BASE_DIR)/../base-hw/src/lib/hw
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NR_OF_CPUS = 4
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# include less specific configuration
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include $(REP_DIR)/lib/mk/core-hw.inc
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@ -23,8 +23,19 @@
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mrs x0, mpidr_el1
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and x0, x0, #0b11111111
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cbz x0, _crt0_fill_bss_zero
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/**
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* Hack for Qemu, which starts all cpus at once
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*/
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1:
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ldr x1, =_crt0_qemu_start_secondary_cpus
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ldr w1, [x1]
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cbnz w1, _crt0_enable_fpu
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wfe
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b _start
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b 1b
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.global _crt0_qemu_start_secondary_cpus
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_crt0_qemu_start_secondary_cpus:
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.long 0
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/***************************
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@ -32,12 +43,12 @@
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***************************/
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_crt0_fill_bss_zero:
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ldr x0, =_bss_start
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ldr x1, =_bss_end
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ldr x1, =_bss_start
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ldr x2, =_bss_end
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1:
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cmp x1, x0
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cmp x2, x1
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b.eq _crt0_enable_fpu
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str xzr, [x0], #8
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str xzr, [x1], #8
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b 1b
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@ -45,20 +56,30 @@
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** Enable FPU **
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****************/
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.global _crt0_enable_fpu
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_crt0_enable_fpu:
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mov x0, #0b11
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lsl x0, x0, #20
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msr cpacr_el1, x0
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mov x1, #0b11
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lsl x1, x1, #20
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msr cpacr_el1, x1
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/**********************
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** Initialize stack **
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**********************/
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ldr x0, =_crt0_start_stack
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mov sp, x0
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.set STACK_SIZE, 0x2000
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ldr x1, =_crt0_start_stack
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ldr x2, [x1]
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mul x0, x0, x2
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add x1, x1, x0
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mov sp, x1
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bl init
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.p2align 4
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.space 0x4000
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.rept NR_OF_CPUS
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.space STACK_SIZE
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.endr
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_crt0_start_stack:
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.long STACK_SIZE
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@ -21,7 +21,12 @@
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namespace Board {
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using namespace Hw::Imx8q_evk_board;
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using Cpu = Hw::Arm_64_cpu;
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struct Cpu : Hw::Arm_64_cpu
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{
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static void wake_up_all_cpus(void*);
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};
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using Hw::Pic;
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};
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@ -28,3 +28,22 @@ Bootstrap::Platform::Board::Board()
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{
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::Board::Pic pic {};
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}
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void Board::Cpu::wake_up_all_cpus(void * ip)
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{
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enum Function_id { CPU_ON = 0xC4000003 };
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unsigned long result = 0;
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for (unsigned i = 1; i < NR_OF_CPUS; i++) {
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asm volatile("mov x0, %1 \n"
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"mov x1, %2 \n"
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"mov x2, %3 \n"
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"mov x3, %2 \n"
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"smc #0 \n"
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"mov %0, x0 \n"
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: "=r" (result) : "r" (CPU_ON), "r" (i), "r" (ip)
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: "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
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"x8", "x9", "x10", "x11", "x12", "x13", "x14");
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}
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}
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@ -23,7 +23,7 @@ namespace Board {
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struct Cpu : Hw::Arm_64_cpu
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{
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static void wake_up_all_cpus(void*);
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static void wake_up_all_cpus(void*) {}
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};
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struct Pic { }; /* dummy object */
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@ -46,4 +46,6 @@ void Cpu::trigger_ip_interrupt()
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}
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Cpu::Ipi::Ipi(Cpu & cpu) : Irq(Board::Pic::IPI, cpu), cpu(cpu) { }
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Cpu::Ipi::Ipi(Cpu & cpu)
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: Irq(Board::Pic::IPI, cpu), cpu(cpu) {
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cpu.pic().unmask(Board::Pic::IPI, cpu.id()); }
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@ -31,7 +31,7 @@ class Kernel::Lock
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enum State { UNLOCKED, LOCKED };
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State volatile _locked { UNLOCKED };
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int volatile _locked { UNLOCKED };
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unsigned volatile _current_cpu { INVALID };
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public:
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@ -83,7 +83,7 @@ struct Genode::Cpu : Hw::Arm_64_cpu
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/**
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* Return kernel name of the executing CPU
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*/
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static unsigned executing_id() { return 0; }
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static unsigned executing_id() { return Cpu::Mpidr::read() & 0xff; }
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static void clean_data_cache_by_virt_region(addr_t, size_t);
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@ -77,6 +77,7 @@ _kernel_entry:
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.global idle_thread_main
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idle_thread_main:
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wfi
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b idle_thread_main
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@ -161,6 +161,7 @@ class Hw::Pic
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SYSTEM_REGISTER(32, Icc_pmr_el1, "S3_0_C4_C6_0");
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SYSTEM_REGISTER(32, Icc_igrpen1_el1, "S3_0_C12_C12_7");
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SYSTEM_REGISTER(32, Icc_eoir1_el1, "S3_0_C12_C12_1");
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SYSTEM_REGISTER(64, Icc_sgi1r_el1, "S3_0_C12_C11_5");
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void init()
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{
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@ -257,6 +258,11 @@ class Hw::Pic
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}
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void irq_mode(unsigned, unsigned, unsigned) { }
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void send_ipi(unsigned const cpu_id)
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{
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Cpu_interface::Icc_sgi1r_el1::write(1ULL << cpu_id);
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}
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};
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#undef SYSTEM_REGISTER
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@ -97,6 +97,8 @@ struct Hw::Arm_64_cpu
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struct Attr3 : Bitfield<24, 8> {};
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);
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SYSTEM_REGISTER(64, Mpidr, mpidr_el1);
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SYSTEM_REGISTER(32, Pmuserenr_el0, pmuserenr_el0);
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SYSTEM_REGISTER(64, Scr, scr_el3,
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@ -178,6 +180,37 @@ struct Hw::Arm_64_cpu
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using Cntp_ctl = Cntp_ctl_el0;
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using Cntpct = Cntpct_el0;
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using Cntp_tval = Cntp_tval_el0;
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static inline void wait_for_xchg(volatile int * addr,
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int new_value,
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int expected_value)
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{
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asm volatile(
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/* check if load value of 'addr' is as expected */
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"1: ldxr w7, [%0] \n"
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"cmp w7, %w2 \n"
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"b.eq 2f \n"
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/* if not, wait for other CPU to send us an event */
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"wfe \n"
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"b.ne 1b \n"
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/* if yes, attempt to write 'new_value' to 'addr' */
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"2: stxr w7, %w1, [%0]\n"
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/* if write failed, restart */
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"cbnz w7, 1b \n"
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"dmb #0 \n"
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:: "r"(addr), "r"(new_value), "r"(expected_value) : "cc", "x7");
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}
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static inline void wakeup_waiting_cpus()
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{
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asm volatile(
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"dsb #0 \n"
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"sev \n"
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);
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}
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};
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