Let OMAP4 SD-card driver use DMA and interrupts
With this patch, the driver code gets complemented with DMA support. The support for master DMA, in turn, cleared the way for using interrupts to wait for the completion of transfers, which largely relieves the CPU compared to the polling PIO mode. Consequently, the new version has a much lower CPU footprint. In the current version, both modes of operation PIO and DMA are functional. However, PIO mode is retained for benchmarking purposes only and will possibly be removed to keep the driver simple. It is disabled in the driver's 'main.cc'.
This commit is contained in:
Norman Feske
parent
e9497a183f
commit
0f6110ea97
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@ -57,12 +57,16 @@ class Block::Omap4_driver : public Block::Driver
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/* hsmmc controller instance */
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Omap4_hsmmc_controller _controller;
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bool const _use_dma;
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public:
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Omap4_driver()
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Omap4_driver(bool use_dma)
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:
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_mmchs1_mmio(MMCHS1_MMIO_BASE, MMCHS1_MMIO_SIZE),
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_controller((addr_t)_mmchs1_mmio.local_addr<void>(), _delayer)
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_controller((addr_t)_mmchs1_mmio.local_addr<void>(),
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_delayer, use_dma),
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_use_dma(use_dma)
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{
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Sd_card::Card_info const card_info = _controller.card_info();
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@ -102,17 +106,19 @@ class Block::Omap4_driver : public Block::Driver
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Genode::size_t block_count,
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Genode::addr_t phys)
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{
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throw Io_error();
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if (!_controller.read_blocks_dma(block_number, block_count, phys))
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throw Io_error();
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}
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void write_dma(Genode::size_t block_number,
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Genode::size_t block_count,
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Genode::addr_t phys)
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{
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throw Io_error();
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if (!_controller.write_blocks_dma(block_number, block_count, phys))
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throw Io_error();
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}
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bool dma_enabled() { return false; }
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bool dma_enabled() { return _use_dma; }
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};
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#endif /* _DRIVER_H_ */
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@ -30,7 +30,8 @@ int main(int argc, char **argv)
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{
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Block::Driver *create()
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{
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return new (env()->heap()) Block::Omap4_driver();
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bool use_dma = true;
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return new (env()->heap()) Block::Omap4_driver(use_dma);
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}
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void destroy(Block::Driver *driver)
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@ -9,6 +9,8 @@
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/* Genode includes */
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#include <util/mmio.h>
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#include <os/attached_ram_dataspace.h>
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#include <irq_session/connection.h>
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/* local includes */
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#include <sd_card.h>
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@ -54,6 +56,11 @@ struct Mmchs : Genode::Mmio
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struct Dw8 : Bitfield<5, 1> { };
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/**
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* Master master slave selection (set if master DMA)
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*/
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struct Dma_mns : Bitfield<20, 1> { };
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};
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/**
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@ -98,6 +105,11 @@ struct Mmchs : Genode::Mmio
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* Auto-CMD12 enable
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*/
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struct Acen : Bitfield<2, 1> { };
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/**
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* DMA enable
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*/
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struct De : Bitfield<0, 1> { };
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};
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/**
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@ -262,6 +274,11 @@ struct Mmchs : Genode::Mmio
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*/
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struct Cc_enable : Bitfield<0, 1> { };
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/**
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* Transfer completed
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*/
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struct Tc_enable : Bitfield<1, 1> { };
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/**
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* Card interrupt
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*/
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@ -273,7 +290,14 @@ struct Mmchs : Genode::Mmio
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struct Cto_enable : Bitfield<16, 1> { };
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};
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struct Ise : Register<0x238, 32> { };
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struct Ise : Register<0x238, 32>
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{
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/*
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* The naming follows the lines of the 'Ie' register
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*/
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struct Tc_sigen : Bitfield<1, 1> { };
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struct Cto_sigen : Bitfield<16, 1> { };
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};
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/**
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* Capabilities
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@ -284,6 +308,27 @@ struct Mmchs : Genode::Mmio
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struct Vs18 : Bitfield<26, 1> { };
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};
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/**
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* ADMA system address
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*
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* Base address of the ADMA descriptor table
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*/
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struct Admasal : Register<0x258, 32> { };
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/**
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* ADMA descriptor layout
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*/
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struct Adma_desc : Genode::Register<64>
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{
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struct Valid : Bitfield<0, 1> { };
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struct Ent : Bitfield<1, 1> { };
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struct Int : Bitfield<2, 1> { };
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struct Act1 : Bitfield<4, 1> { };
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struct Act2 : Bitfield<5, 1> { };
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struct Length : Bitfield<16, 16> { };
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struct Address : Bitfield<32, 32> { };
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};
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bool reset_cmd_line(Delayer &delayer)
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{
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write<Sysctl::Src>(1);
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@ -437,6 +482,17 @@ struct Omap4_hsmmc_controller : private Mmchs, public Sd_card::Host_controller
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Delayer &_delayer;
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Sd_card::Card_info _card_info;
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bool const _use_dma;
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/*
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* DMA memory for holding the ADMA descriptor table
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*/
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enum { ADMA_DESC_MAX_ENTRIES = 1024 };
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Genode::Attached_ram_dataspace _adma_desc_ds;
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Adma_desc::access_t * const _adma_desc;
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Genode::addr_t const _adma_desc_phys;
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Genode::Irq_connection _irq;
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Sd_card::Card_info _init()
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{
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@ -536,19 +592,174 @@ struct Omap4_hsmmc_controller : private Mmchs, public Sd_card::Host_controller
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throw Detection_failed();
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}
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/* enable master DMA */
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write<Con::Dma_mns>(1);
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/* enable IRQs */
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write<Ie::Tc_enable>(1);
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write<Ie::Cto_enable>(1);
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write<Ise::Tc_sigen>(1);
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write<Ise::Cto_sigen>(1);
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return card_info;
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}
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/**
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* Marshal ADMA descriptors according to block request
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*
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* \return false if block request is too large
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*/
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bool _setup_adma_descriptor_table(size_t block_count,
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Genode::addr_t out_buffer_phys)
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{
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using namespace Sd_card;
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/* reset ADMA offset to first descriptor */
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write<Admasal>(_adma_desc_phys);
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enum { BLOCK_SIZE = 512 /* bytes */ };
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size_t const max_adma_request_size = 64*1024 - 4; /* bytes */
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/*
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* sanity check
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*
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* XXX An alternative to this sanity check would be to expose
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* the maximum DMA transfer size to the driver and let the
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* driver partition large requests into ones that are
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* supported by the controller.
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*/
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if (block_count*BLOCK_SIZE > max_adma_request_size*ADMA_DESC_MAX_ENTRIES) {
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PERR("Block request too large");
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return false;
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}
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/*
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* Each ADMA descriptor can transfer up to MAX_ADMA_REQUEST_SIZE
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* bytes. If the request is larger, we generate a list of ADMA
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* descriptors.
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*/
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size_t const total_bytes = block_count*BLOCK_SIZE;
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/* number of bytes for which descriptors have been created */
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addr_t consumed_bytes = 0;
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for (int index = 0; consumed_bytes < total_bytes; index++) {
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size_t const remaining_bytes = total_bytes - consumed_bytes;
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/* clamp current request to maximum ADMA request size */
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size_t const curr_bytes = Genode::min(max_adma_request_size,
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remaining_bytes);
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/*
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* Assemble new ADMA descriptor
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*/
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Adma_desc::access_t desc = 0;
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Adma_desc::Address::set(desc, out_buffer_phys + consumed_bytes);
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Adma_desc::Length::set(desc, curr_bytes);
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/* set action to transfer */
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Adma_desc::Act1::set(desc, 0);
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Adma_desc::Act2::set(desc, 1);
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Adma_desc::Valid::set(desc, 1);
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/*
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* Let the last descriptor generate transfer-complete interrupt
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*/
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if (consumed_bytes + curr_bytes == total_bytes)
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Adma_desc::Ent::set(desc, 1);
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/* install descriptor into ADMA descriptor table */
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_adma_desc[index] = desc;
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consumed_bytes += curr_bytes;
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}
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return true;
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}
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bool _wait_for_transfer_complete()
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{
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if (!wait_for<Stat::Tc>(1, _delayer, 1000*1000, 0)
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&& !wait_for<Stat::Tc>(1, _delayer)) {
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PERR("Stat::Tc timed out");
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return false;
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}
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/* clear transfer-completed bit */
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write<Stat::Tc>(1);
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return true;
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}
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bool _wait_for_bre()
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{
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if (!wait_for<Pstate::Bre>(1, _delayer, 1000*1000, 0)
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&& !wait_for<Pstate::Bre>(1, _delayer)) {
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PERR("Pstate::Bre timed out");
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return false;
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}
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return true;
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}
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bool _wait_for_bwe()
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{
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if (!wait_for<Pstate::Bwe>(1, _delayer, 1000*1000, 0)
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&& !wait_for<Pstate::Bwe>(1, _delayer)) {
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PERR("Pstate::Bwe timed out");
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return false;
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}
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return true;
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}
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bool _wait_for_transfer_complete_irq()
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{
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/*
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* XXX For now, the driver works fully synchronous. We merely use
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* the interrupt mechanism to yield CPU time to concurrently
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* running processes.
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*/
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for (;;) {
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_irq.wait_for_irq();
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/* check for transfer completion */
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if (read<Stat::Tc>() == 1) {
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/* clear transfer-completed bit */
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write<Stat::Tc>(1);
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if (read<Stat>() != 0)
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PWRN("unexpected state (Stat: 0x%x Blen: 0x%x Nblk: %d)",
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read<Stat>(), read<Blk::Blen>(), read<Blk::Nblk>());
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return true;
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}
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PWRN("unexpected interrupt, Stat: 0x%08x", read<Stat>());
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}
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}
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public:
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enum { IRQ_NUMBER = 83 + 32 };
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/**
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* Constructor
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*
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* \param mmio_base local base address of MMIO registers
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*/
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Omap4_hsmmc_controller(Genode::addr_t const mmio_base, Delayer &delayer)
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Omap4_hsmmc_controller(Genode::addr_t const mmio_base, Delayer &delayer,
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bool use_dma)
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:
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Mmchs(mmio_base), _delayer(delayer), _card_info(_init())
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Mmchs(mmio_base), _delayer(delayer), _card_info(_init()),
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_use_dma(use_dma),
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_adma_desc_ds(Genode::env()->ram_session(),
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ADMA_DESC_MAX_ENTRIES*sizeof(Adma_desc::access_t),
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false),
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_adma_desc(_adma_desc_ds.local_addr<Adma_desc::access_t>()),
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_adma_desc_phys(Genode::Dataspace_client(_adma_desc_ds.cap()).phys_addr()),
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_irq(IRQ_NUMBER)
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{ }
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@ -580,9 +791,13 @@ struct Omap4_hsmmc_controller : private Mmchs, public Sd_card::Host_controller
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Cmd::Msbs::set(cmd);
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if (command.index == Sd_card::Read_multiple_block::INDEX
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|| command.index == Sd_card::Write_multiple_block::INDEX)
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|| command.index == Sd_card::Write_multiple_block::INDEX) {
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Cmd::Acen::set(cmd);
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if (_use_dma)
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Cmd::De::set(cmd);
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}
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/* set data-direction bit depending on the command */
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bool const read = command.transfer == Sd_card::TRANSFER_READ;
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Cmd::Ddir::set(cmd, read ? Cmd::Ddir::READ : Cmd::Ddir::WRITE);
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@ -662,39 +877,6 @@ struct Omap4_hsmmc_controller : private Mmchs, public Sd_card::Host_controller
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return Sd_card::Send_relative_addr::Response::Rca::get(read<Rsp10>());
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}
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bool _wait_for_transfer_complete()
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{
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if (!wait_for<Stat::Tc>(1, _delayer, 1000*1000, 0)
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&& !wait_for<Stat::Tc>(1, _delayer)) {
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PERR("Stat::Tc timed out");
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return false;
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}
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/* clear transfer-completed bit */
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write<Stat::Tc>(1);
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return true;
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}
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bool _wait_for_bre()
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{
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if (!wait_for<Pstate::Bre>(1, _delayer, 1000*1000, 0)
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&& !wait_for<Pstate::Bre>(1, _delayer)) {
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PERR("Pstate::Bre timed out");
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return false;
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}
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return true;
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}
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bool _wait_for_bwe()
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{
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if (!wait_for<Pstate::Bwe>(1, _delayer, 1000*1000, 0)
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&& !wait_for<Pstate::Bwe>(1, _delayer)) {
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PERR("Pstate::Bwe timed out");
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return false;
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}
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return true;
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}
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/**
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* Read data blocks from SD card
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*
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@ -708,7 +890,7 @@ struct Omap4_hsmmc_controller : private Mmchs, public Sd_card::Host_controller
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write<Blk::Nblk>(block_count);
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if (!issue_command(Read_multiple_block(block_number))) {
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PERR("Read_multiple_block failed");
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PERR("Read_multiple_block failed, Stat: 0x%08x", read<Stat>());
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return false;
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}
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@ -754,6 +936,52 @@ struct Omap4_hsmmc_controller : private Mmchs, public Sd_card::Host_controller
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return _wait_for_transfer_complete();
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}
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/**
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* Read data blocks from SD card via master DMA
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*
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* \return true on success
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*/
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bool read_blocks_dma(size_t block_number, size_t block_count,
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Genode::addr_t out_buffer_phys)
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{
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using namespace Sd_card;
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write<Blk::Blen>(0x200);
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write<Blk::Nblk>(block_count);
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_setup_adma_descriptor_table(block_count, out_buffer_phys);
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if (!issue_command(Read_multiple_block(block_number))) {
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PERR("Read_multiple_block failed, Stat: 0x%08x", read<Stat>());
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return false;
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}
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return _wait_for_transfer_complete_irq();
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}
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/**
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* Write data blocks to SD card via master DMA
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*
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* \return true on success
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*/
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bool write_blocks_dma(size_t block_number, size_t block_count,
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Genode::addr_t buffer_phys)
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{
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using namespace Sd_card;
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write<Blk::Blen>(0x200);
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write<Blk::Nblk>(block_count);
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_setup_adma_descriptor_table(block_count, buffer_phys);
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if (!issue_command(Write_multiple_block(block_number))) {
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PERR("Write_multiple_block failed");
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return false;
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}
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return _wait_for_transfer_complete_irq();
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}
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};
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#endif /* _MMCHS_H_ */
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