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hw: unify board definitions of bootstrap/core 

Ref #3326
This commit is contained in:
Stefan Kalkowski 2019-05-16 13:42:46 +02:00 committed by Christian Helmuth
parent 8eecb39792
commit 054df95ea4
42 changed files with 527 additions and 367 deletions
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17
repos/base-hw/src/bootstrap/spec/arndale/board.h
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@ -14,24 +14,11 @@
#ifndef _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_
#include <drivers/defs/arndale.h>
#include <drivers/uart/exynos.h>
#include <hw/spec/arm/cortex_a15.h>
#include <hw/spec/arm/arndale_board.h>
#include <hw/spec/arm/lpae.h>
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Board {
using namespace Arndale;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Exynos_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_CLOCK = UART_2_CLOCK,
};
}
namespace Board { using namespace Hw::Arndale_board; }
#endif /* _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_ */

11
repos/base-hw/src/bootstrap/spec/imx53_qsb/board.h
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@ -14,21 +14,14 @@
#ifndef _SRC__BOOTSTRAP__SPEC__IMX53_QSB__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__IMX53_QSB__BOARD_H_
#include <drivers/defs/imx53_qsb.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/imx53_qsb_board.h>
#include <hw/spec/arm/imx_tzic.h>
#include <spec/arm/cortex_a8_page_table.h>
#include <spec/arm/cpu.h>
namespace Board {
using namespace Imx53_qsb;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* ignored value */
};
using namespace Hw::Imx53_qsb_board;
bool secure_irq(unsigned irq);
}

17
repos/base-hw/src/bootstrap/spec/imx6q_sabrelite/board.h
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@ -14,29 +14,16 @@
#ifndef _SRC__BOOTSTRAP__SPEC__IMX6Q_SABRELITE__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__IMX6Q_SABRELITE__BOARD_H_
#include <drivers/defs/imx6q_sabrelite.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <hw/spec/arm/imx6q_sabrelite_board.h>
#include <spec/arm/cortex_a9_actlr.h>
#include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Board {
using namespace Imx6q_sabrelite;
using namespace Hw::Imx6q_sabrelite_board;
struct L2_cache;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_SIZE = UART_2_MMIO_SIZE,
UART_CLOCK = 0, /* dummy value, not used */
};
static volatile unsigned long initial_values[][2] {
// (IOMUX Controller)

16
repos/base-hw/src/bootstrap/spec/imx7d_sabre/board.h
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@ -14,25 +14,13 @@
#ifndef _SRC__BOOTSTRAP__SPEC__IMX7_SABRELITE__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__IMX7_SABRELITE__BOARD_H_
#include <drivers/defs/imx7d_sabre.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a15.h>
#include <hw/spec/arm/imx7d_sabre_board.h>
#include <hw/spec/arm/lpae.h>
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Board {
using namespace Imx7d_sabre;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* unsued value */
};
using namespace Hw::Imx7d_sabre_board;
}
#endif /* _SRC__BOOTSTRAP__SPEC__IMX&_SABRELITE__BOARD_H_ */

19
repos/base-hw/src/bootstrap/spec/nit6_solox/board.h
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@ -14,32 +14,18 @@
#ifndef _SRC__BOOTSTRAP__SPEC__NIT6_SOLOX__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__NIT6_SOLOX__BOARD_H_
#include <drivers/defs/nit6_solox.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <hw/spec/arm/nit6_solox_board.h>
#include <spec/arm/cortex_a9_actlr.h>
#include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Board {
using namespace Nit6_solox;
using namespace Hw::Nit6_solox_board;
struct L2_cache;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_SIZE = UART_1_MMIO_SIZE,
UART_CLOCK = 0, /* dummy value, not used */
};
static volatile unsigned long initial_values[][2] {
// (IOMUX Controller)
{ 0x20E006C, 0x0},
{ 0x20E00CC, 0x10},
@ -243,7 +229,6 @@ namespace Board {
};
}
struct Board::L2_cache : Hw::Pl310
{
L2_cache(Genode::addr_t mmio) : Hw::Pl310(mmio)

15
repos/base-hw/src/bootstrap/spec/odroid_xu/board.h
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@ -14,24 +14,13 @@
#ifndef _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_
#include <drivers/defs/odroid_xu.h>
#include <drivers/uart/exynos.h>
#include <hw/spec/arm/cortex_a15.h>
#include <hw/spec/arm/odroid_xu_board.h>
#include <hw/spec/arm/lpae.h>
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Board {
using namespace Odroid_xu;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Exynos_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_CLOCK = UART_2_CLOCK,
};
using namespace Hw::Odroid_xu_board;
}
#endif /* _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_ */

33
repos/base-hw/src/bootstrap/spec/panda/board.h
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@ -1,5 +1,5 @@
/*
* \brief Pbxa9 specific board definitions
* \brief Pandaboard specific definitions
* \author Stefan Kalkowski
* \date 2017-02-20
*/
@ -14,27 +14,15 @@
#ifndef _SRC__BOOTSTRAP__SPEC__PANDA__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__PANDA__BOARD_H_
#include <drivers/defs/panda.h>
#include <drivers/uart/tl16c750.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <hw/spec/arm/panda_trustzone_firmware.h>
#include <hw/spec/arm/panda_board.h>
#include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Board {
using namespace Hw::Panda_board;
class L2_cache;
using namespace Panda;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Tl16c750_uart;
enum {
UART_BASE = TL16C750_3_MMIO_BASE,
UART_CLOCK = TL16C750_CLOCK,
};
}
namespace Bootstrap { struct Actlr; }
@ -42,8 +30,11 @@ namespace Bootstrap { struct Actlr; }
struct Bootstrap::Actlr
{
static void enable_smp() {
Hw::call_panda_firmware(Hw::CPU_ACTLR_SMP_BIT_RAISE, 0); }
static void enable_smp()
{
using namespace Board;
call_panda_firmware(CPU_ACTLR_SMP_BIT_RAISE, 0);
}
static void disable_smp() { /* not implemented */ }
};
@ -71,18 +62,18 @@ class Board::L2_cache : Hw::Pl310
public:
L2_cache(Genode::addr_t mmio) : Hw::Pl310(mmio) {
Hw::call_panda_firmware(Hw::L2_CACHE_AUX_REG, _init_value()); }
call_panda_firmware(L2_CACHE_AUX_REG, _init_value()); }
using Hw::Pl310::invalidate;
void enable()
{
Hw::call_panda_firmware(Hw::L2_CACHE_ENABLE_REG, 1);
call_panda_firmware(L2_CACHE_ENABLE_REG, 1);
Pl310::mask_interrupts();
}
void disable() {
Hw::call_panda_firmware(Hw::L2_CACHE_ENABLE_REG, 0); }
call_panda_firmware(L2_CACHE_ENABLE_REG, 0); }
};
#endif /* _SRC__BOOTSTRAP__SPEC__PANDA__BOARD_H_ */

17
repos/base-hw/src/bootstrap/spec/pbxa9/board.h
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@ -14,10 +14,7 @@
#ifndef _SRC__BOOTSTRAP__SPEC__PBXA9__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__PBXA9__BOARD_H_
#include <drivers/defs/pbxa9.h>
#include <drivers/uart/pl011.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <hw/spec/arm/pbxa9_board.h>
#include <spec/arm/cortex_a9_actlr.h>
#include <spec/arm/cortex_a9_page_table.h>
@ -25,17 +22,7 @@
#include <spec/arm/pic.h>
namespace Board {
using namespace Pbxa9;
using L2_cache = Hw::Pl310;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Pl011_uart;
enum {
UART_BASE = PL011_0_MMIO_BASE,
UART_CLOCK = PL011_0_CLOCK,
};
using namespace Hw::Pbxa9_board;
}
#endif /* _SRC__BOOTSTRAP__SPEC__PBXA9__BOARD_H_ */

16
repos/base-hw/src/bootstrap/spec/riscv/board.h
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@ -14,22 +14,10 @@
#ifndef _SRC__BOOTSTRAP__SPEC__RISCV__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__RISCV__BOARD_H_
#include <hw/spec/riscv/page_table.h>
#include <hw/spec/riscv/uart.h>
#include <drivers/defs/riscv.h>
namespace Bootstrap {
struct Cpu {};
struct Pic {};
}
#include <hw/spec/riscv/board.h>
namespace Board {
using namespace Riscv;
enum { UART_BASE, UART_CLOCK };
struct Serial : Hw::Riscv_uart {
Serial(Genode::addr_t, Genode::size_t, unsigned) {} };
using namespace Hw::Riscv_board;
}
template <typename E, unsigned B, unsigned S>

11
repos/base-hw/src/bootstrap/spec/rpi/board.h
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@ -14,19 +14,12 @@
#ifndef _SRC__BOOTSTRAP__SPEC__RPI__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__RPI__BOARD_H_
#include <drivers/defs/rpi.h>
#include <drivers/uart/pl011.h>
#include <hw/spec/arm/rpi_board.h>
#include <hw/spec/arm/page_table.h>
#include <spec/arm/cpu.h>
namespace Board {
using Serial = Genode::Pl011_uart;
enum {
UART_BASE = Rpi::PL011_0_MMIO_BASE,
UART_CLOCK = Rpi::PL011_0_CLOCK,
};
using namespace Hw::Rpi_board;
}
namespace Bootstrap { struct Pic {}; }

11
repos/base-hw/src/bootstrap/spec/usb_armory/board.h
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@ -14,8 +14,7 @@
#ifndef _SRC__BOOTSTRAP__SPEC__USB_ARMORY__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__USB_ARMORY__BOARD_H_
#include <drivers/defs/usb_armory.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/usb_armory_board.h>
#include <hw/spec/arm/imx_tzic.h>
#include <spec/arm/cortex_a8_page_table.h>
@ -24,13 +23,7 @@
namespace Bootstrap { using Hw::Pic; }
namespace Board {
using namespace Usb_armory;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* ignored value */
};
using namespace Hw::Usb_armory_board;
bool secure_irq(unsigned irq);
}

17
repos/base-hw/src/bootstrap/spec/wand_quad/board.h
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@ -14,29 +14,16 @@
#ifndef _SRC__BOOTSTRAP__SPEC__WAND_QUAD__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__WAND_QUAD__BOARD_H_
#include <drivers/defs/wand_quad.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <hw/spec/arm/wand_quad_board.h>
#include <spec/arm/cortex_a9_actlr.h>
#include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Board {
using namespace Wand_quad;
using namespace Hw::Wand_quad_board;
struct L2_cache;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_SIZE = UART_1_MMIO_SIZE,
UART_CLOCK = 0, /* dummy value, not used */
};
static volatile unsigned long initial_values[][2] {
// (IOMUX Controller)

12
repos/base-hw/src/bootstrap/spec/x86_64/board.h
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@ -14,8 +14,7 @@
#ifndef _SRC__BOOTSTRAP__SPEC__X86_64__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__X86_64__BOARD_H_
#include <drivers/uart/x86_pc.h>
#include <hw/spec/x86_64/pc_board.h>
#include <hw/spec/x86_64/page_table.h>
#include <hw/spec/x86_64/cpu.h>
#include <hw/spec/x86_64/x86_64.h>
@ -26,14 +25,7 @@ namespace Bootstrap {
}
namespace Board {
struct Serial;
enum Dummies { UART_BASE, UART_CLOCK };
using namespace Hw::Pc_board;
}
struct Board::Serial : Genode::X86_uart
{
Serial(Genode::addr_t, Genode::size_t, unsigned);
};
#endif /* _SRC__BOOTSTRAP__SPEC__X86_64__BOARD_H_ */

15
repos/base-hw/src/bootstrap/spec/zynq_qemu/board.h
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@ -14,25 +14,14 @@
#ifndef _SRC__BOOTSTRAP__SPEC__ZYNQ__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__ZYNQ__BOARD_H_
#include <drivers/defs/zynq_qemu.h>
#include <drivers/uart/xilinx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <hw/spec/arm/zynq_qemu_board.h>
#include <spec/arm/cortex_a9_actlr.h>
#include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Board {
using namespace Zynq_qemu;
using L2_cache = Hw::Pl310;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Xilinx_uart;
enum {
UART_BASE = UART_0_MMIO_BASE,
};
using namespace Hw::Zynq_qemu_board;
}
#endif /* _SRC__BOOTSTRAP__SPEC__ZYNQ__BOARD_H_ */

15
repos/base-hw/src/core/spec/arndale/board.h
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@ -14,21 +14,10 @@
#ifndef _CORE__SPEC__ARNDALE__BOARD_H_
#define _CORE__SPEC__ARNDALE__BOARD_H_
/* base includes */
#include <drivers/defs/arndale.h>
#include <drivers/uart/exynos.h>
#include <hw/spec/arm/cortex_a15.h>
#include <hw/spec/arm/arndale_board.h>
namespace Board {
using namespace Arndale;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Exynos_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_CLOCK = UART_2_CLOCK,
};
using namespace Hw::Arndale_board;
static constexpr bool SMP = true;
}

11
repos/base-hw/src/core/spec/imx53_qsb/board.h
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@ -15,17 +15,10 @@
#ifndef _CORE__SPEC__IMX53_QSB__BOARD_H_
#define _CORE__SPEC__IMX53_QSB__BOARD_H_
#include <drivers/defs/imx53_qsb.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/imx53_qsb_board.h>
namespace Board {
using namespace Imx53_qsb;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* ignored value */
};
using namespace Hw::Imx53_qsb_board;
static constexpr bool SMP = false;
}

18
repos/base-hw/src/core/spec/imx6q_sabrelite/board.h
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@ -14,23 +14,13 @@
#ifndef _CORE__SPEC__IMX6Q_SABRELITE__BOARD_H_
#define _CORE__SPEC__IMX6Q_SABRELITE__BOARD_H_
/* base includes */
#include <drivers/defs/imx6q_sabrelite.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <hw/spec/arm/imx6q_sabrelite_board.h>
namespace Board {
using namespace Imx6q_sabrelite;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using L2_cache = Hw::Pl310;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_CLOCK = 0, /* dummy value, not used */
};
using namespace Hw::Imx6q_sabrelite_board;
using L2_cache = Hw::Pl310;
static constexpr bool SMP = true;

17
repos/base-hw/src/core/spec/imx7d_sabre/board.h
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@ -14,22 +14,11 @@
#ifndef _CORE__SPEC__IMX7D_SABRE__BOARD_H_
#define _CORE__SPEC__IMX7D_SABRE__BOARD_H_
/* base includes */
#include <drivers/defs/imx7d_sabre.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a15.h>
#include <hw/spec/arm/imx7d_sabre_board.h>
namespace Board {
using namespace Imx7d_sabre;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* unused value */
};
using namespace Hw::Imx7d_sabre_board;
static constexpr bool SMP = true;
}

17
repos/base-hw/src/core/spec/nit6_solox/board.h
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@ -14,23 +14,12 @@
#ifndef _CORE__SPEC__NIT6_SOLOX__BOARD_H_
#define _CORE__SPEC__NIT6_SOLOX__BOARD_H_
/* base includes */
#include <drivers/defs/nit6_solox.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <hw/spec/arm/nit6_solox_board.h>
namespace Board {
using namespace Nit6_solox;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using L2_cache = Hw::Pl310;
using Serial = Genode::Imx_uart;
using namespace Hw::Nit6_solox_board;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* dummy value, not used */
};
using L2_cache = Hw::Pl310;
static constexpr bool SMP = true;

15
repos/base-hw/src/core/spec/odroid_xu/board.h
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@ -14,21 +14,10 @@
#ifndef _CORE__SPEC__ODROID_XU__BOARD_H_
#define _CORE__SPEC__ODROID_XU__BOARD_H_
/* base includes */
#include <drivers/defs/odroid_xu.h>
#include <drivers/uart/exynos.h>
#include <hw/spec/arm/cortex_a15.h>
#include <hw/spec/arm/odroid_xu_board.h>
namespace Board {
using namespace Odroid_xu;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Exynos_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_CLOCK = UART_2_CLOCK,
};
using namespace Hw::Odroid_xu_board;
static constexpr bool SMP = true;
}

20
repos/base-hw/src/core/spec/panda/board.h
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@ -15,25 +15,11 @@
#ifndef _CORE__SPEC__PANDA__BOARD_H_
#define _CORE__SPEC__PANDA__BOARD_H_
/* base includes */
#include <drivers/defs/panda.h>
#include <drivers/uart/tl16c750.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <hw/spec/arm/panda_trustzone_firmware.h>
#include <hw/spec/arm/panda_board.h>
namespace Board {
using namespace Panda;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Tl16c750_uart;
enum {
UART_BASE = TL16C750_3_MMIO_BASE,
UART_CLOCK = TL16C750_CLOCK,
};
using namespace Hw::Panda_board;
static constexpr bool SMP = true;
class L2_cache : public Hw::Pl310

18
repos/base-hw/src/core/spec/pbxa9/board.h
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@ -14,24 +14,10 @@
#ifndef _CORE__SPEC__PBXA9__BOARD_H_
#define _CORE__SPEC__PBXA9__BOARD_H_
/* base includes */
#include <drivers/defs/pbxa9.h>
#include <drivers/uart/pl011.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <hw/spec/arm/pbxa9_board.h>
namespace Board {
using namespace Pbxa9;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using L2_cache = Hw::Pl310;
using Serial = Genode::Pl011_uart;
enum {
UART_BASE = PL011_0_MMIO_BASE,
UART_CLOCK = PL011_0_CLOCK,
};
using namespace Hw::Pbxa9_board;
static constexpr bool SMP = true;

6
repos/base-hw/src/core/spec/riscv/board.h
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@ -14,12 +14,10 @@
#ifndef _CORE__SPEC__RISCV__BOARD_H_
#define _CORE__SPEC__RISCV__BOARD_H_
#include <hw/spec/riscv/uart.h>
#include <hw/spec/riscv/board.h>
namespace Board {
enum { UART_BASE, UART_CLOCK };
struct Serial : Hw::Riscv_uart {
Serial(Genode::addr_t, Genode::size_t, unsigned) {} };
using namespace Hw::Riscv_board;
}
#endif /* _CORE__SPEC__RISCV__BOARD_H_ */

12
repos/base-hw/src/core/spec/rpi/board.h
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@ -15,18 +15,10 @@
#ifndef _CORE__SPEC__RPI__BOARD_H_
#define _CORE__SPEC__RPI__BOARD_H_
#include <drivers/defs/rpi.h>
#include <drivers/uart/pl011.h>
#include <hw/spec/arm/rpi_board.h>
namespace Board {
using namespace Rpi;
using Serial = Genode::Pl011_uart;
enum {
UART_BASE = Rpi::PL011_0_MMIO_BASE,
UART_CLOCK = Rpi::PL011_0_CLOCK,
};
using namespace Hw::Rpi_board;
static constexpr bool SMP = false;
};

11
repos/base-hw/src/core/spec/usb_armory/board.h
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@ -15,17 +15,10 @@
#ifndef _CORE__SPEC__USB_ARMORY__BOARD_H_
#define _CORE__SPEC__USB_ARMORY__BOARD_H_
#include <drivers/defs/usb_armory.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/usb_armory_board.h>
namespace Board {
using namespace Usb_armory;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* dummy value, not used */
};
using namespace Hw::Usb_armory_board;
static constexpr bool SMP = false;
}

19
repos/base-hw/src/core/spec/wand_quad/board.h
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@ -15,24 +15,13 @@
#ifndef _CORE__SPEC__WAND_QUAD__BOARD_H_
#define _CORE__SPEC__WAND_QUAD__BOARD_H_
/* base includes */
#include <drivers/defs/wand_quad.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <hw/spec/arm/wand_quad_board.h>
namespace Board {
using namespace Wand_quad;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using namespace Hw::Wand_quad_board;
using L2_cache = Hw::Pl310;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* dummy value, not used */
};
static constexpr bool SMP = true;
L2_cache & l2_cache();

10
repos/base-hw/src/core/spec/x86_64/board.h
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@ -14,11 +14,10 @@
#ifndef _CORE__SPEC__X86_64__BOARD_H_
#define _CORE__SPEC__X86_64__BOARD_H_
#include <drivers/uart/x86_pc.h>
#include <hw/spec/x86_64/pc_board.h>
namespace Board {
struct Serial;
enum Dummies { UART_BASE, UART_CLOCK };
using namespace Hw::Pc_board;
enum {
VECTOR_REMAP_BASE = 48,
@ -28,9 +27,4 @@ namespace Board {
};
}
struct Board::Serial : Genode::X86_uart {
Serial(Genode::addr_t, Genode::size_t, unsigned);
};
#endif /* _CORE__SPEC__X86_64__BOARD_H_ */

16
repos/base-hw/src/core/spec/zynq_qemu/board.h
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@ -16,22 +16,10 @@
#ifndef _CORE__SPEC__ZYNQ_QEMU__BOARD_H_
#define _CORE__SPEC__ZYNQ_QEMU__BOARD_H_
/* base includes */
#include <drivers/defs/zynq_qemu.h>
#include <drivers/uart/xilinx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <hw/spec/arm/zynq_qemu_board.h>
namespace Board {
using namespace Zynq_qemu;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using L2_cache = Hw::Pl310;
using Serial = Genode::Xilinx_uart;
enum {
UART_BASE = UART_0_MMIO_BASE,
};
using namespace Hw::Zynq_qemu_board;
static constexpr bool SMP = true;

33
repos/base-hw/src/include/hw/spec/arm/arndale_board.h Normal file
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@ -0,0 +1,33 @@
/*
* \brief Arndale specific board definitions
* \author Stefan Kalkowski
* \date 2019-05-15
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__ARNDALE_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__ARNDALE_BOARD_H_
#include <drivers/defs/arndale.h>
#include <drivers/uart/exynos.h>
#include <hw/spec/arm/cortex_a15.h>
namespace Hw::Arndale_board {
using namespace Arndale;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Exynos_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_CLOCK = UART_2_CLOCK,
};
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__ARNDALE_BOARD_H_ */

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repos/base-hw/src/include/hw/spec/arm/imx53_qsb_board.h Normal file
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@ -0,0 +1,30 @@
/*
* \brief i.MX53 Quickstart board definitions
* \author Stefan Kalkowski
* \date 2019-05-15
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__IMX53_QSB_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__IMX53_QSB_BOARD_H_
#include <drivers/defs/imx53_qsb.h>
#include <drivers/uart/imx.h>
namespace Hw::Imx53_qsb_board {
using namespace Imx53_qsb;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* ignored value */
};
}
#endif /* _SRC__INCLUDE__HW__SPEC__IMX53_QSB_BOARD_H_ */

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repos/base-hw/src/include/hw/spec/arm/imx6q_sabrelite_board.h Normal file
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@ -0,0 +1,36 @@
/*
* \brief i.MX6Quad Sabrelite specific board definitions
* \author Stefan Kalkowski
* \date 2019-05-16
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__IMX6Q_SABRELITE_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__IMX6Q_SABRELITE_BOARD_H_
#include <drivers/defs/imx6q_sabrelite.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Hw::Imx6q_sabrelite_board {
using namespace Imx6q_sabrelite;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_SIZE = UART_2_MMIO_SIZE,
UART_CLOCK = 0, /* dummy value, not used */
};
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__IMX6Q_SABRELITE_BOARD_H_ */

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repos/base-hw/src/include/hw/spec/arm/imx7d_sabre_board.h Normal file
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@ -0,0 +1,35 @@
/*
* \brief Imx7 Sabrelite specific board definitions
* \author Stefan Kalkowski
* \date 2018-11-07
*/
/*
* Copyright (C) 2018 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__IMX7_SABRELITE_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__IMX7_SABRELITE_BOARD_H_
#include <drivers/defs/imx7d_sabre.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a15.h>
namespace Hw::Imx7d_sabre_board {
using namespace Imx7d_sabre;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* unsued value */
};
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__IMX7_SABRELITE_BOARD_H_ */

36
repos/base-hw/src/include/hw/spec/arm/nit6_solox_board.h Normal file
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@ -0,0 +1,36 @@
/*
* \brief Nit6 SOLOX specific board definitions
* \author Stefan Kalkowski
* \date 2019-05-16
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__NIT6_SOLOX_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__NIT6_SOLOX_BOARD_H_
#include <drivers/defs/nit6_solox.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Hw::Nit6_solox_board {
using namespace Nit6_solox;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_SIZE = UART_1_MMIO_SIZE,
UART_CLOCK = 0, /* dummy value, not used */
};
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__NIT6_SOLOX_BOARD_H_ */

33
repos/base-hw/src/include/hw/spec/arm/odroid_xu_board.h Normal file
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@ -0,0 +1,33 @@
/*
* \brief Odroid XU specific board definitions
* \author Stefan Kalkowski
* \date 2019-05-16
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__ODROID_XU_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__ODROID_XU_BOARD_H_
#include <drivers/defs/odroid_xu.h>
#include <drivers/uart/exynos.h>
#include <hw/spec/arm/cortex_a15.h>
namespace Hw::Odroid_xu_board {
using namespace Odroid_xu;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Exynos_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_CLOCK = UART_2_CLOCK,
};
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__ODROID_XU_BOARD_H_ */

28
repos/base-hw/src/include/hw/spec/arm/panda_trustzone_firmware.h → repos/base-hw/src/include/hw/spec/arm/panda_board.h
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@ -1,22 +1,34 @@
/*
* \brief Pandaboard's TrustZone firmware frontend
* \author Stefan Kalkowski
* \date 2017-02-02
* \brief Pandaboard specific definitions
* \author Stefan Kalkowski
* \date 2019-05-16
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__LIB__HW__SPEC__ARM__PANDA_TRUSTZONE_FIRMWARE_H_
#define _SRC__LIB__HW__SPEC__ARM__PANDA_TRUSTZONE_FIRMWARE_H_
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__PANDA_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__PANDA_BOARD_H_
#include <base/stdint.h>
#include <drivers/defs/panda.h>
#include <drivers/uart/tl16c750.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Hw {
namespace Hw::Panda_board {
using namespace Panda;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Tl16c750_uart;
enum {
UART_BASE = TL16C750_3_MMIO_BASE,
UART_CLOCK = TL16C750_CLOCK,
};
enum Panda_firmware_opcodes {
CPU_ACTLR_SMP_BIT_RAISE = 0x25,
@ -38,4 +50,4 @@ namespace Hw {
}
}
#endif /* _SRC__LIB__HW__SPEC__ARM__PANDA_TRUSTZONE_FIRMWARE_H_ */
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__PANDA_BOARD_H_ */

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repos/base-hw/src/include/hw/spec/arm/pbxa9_board.h Normal file
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@ -0,0 +1,35 @@
/*
* \brief Pbxa9 specific board definitions
* \author Stefan Kalkowski
* \date 2019-05-16
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__PBXA9_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__PBXA9_BOARD_H_
#include <drivers/defs/pbxa9.h>
#include <drivers/uart/pl011.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Hw::Pbxa9_board {
using namespace Pbxa9;
using L2_cache = Hw::Pl310;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Pl011_uart;
enum {
UART_BASE = PL011_0_MMIO_BASE,
UART_CLOCK = PL011_0_CLOCK,
};
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__PBXA9_BOARD_H_ */

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repos/base-hw/src/include/hw/spec/arm/rpi_board.h Normal file
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@ -0,0 +1,31 @@
/*
* \brief Raspberry PI specific board definitions
* \author Stefan Kalkowski
* \date 2019-05-16
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__RPI_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__RPI_BOARD_H_
#include <drivers/defs/rpi.h>
#include <drivers/uart/pl011.h>
namespace Hw::Rpi_board {
using namespace Rpi;
using Serial = Genode::Pl011_uart;
enum {
UART_BASE = Rpi::PL011_0_MMIO_BASE,
UART_CLOCK = Rpi::PL011_0_CLOCK,
};
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__RPI_BOARD_H_ */

31
repos/base-hw/src/include/hw/spec/arm/usb_armory_board.h Normal file
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@ -0,0 +1,31 @@
/*
* \brief USB armory board definitions
* \author Stefan Kalkowski
* \date 2019-05-15
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__USB_ARMORY_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__USB_ARMORY_BOARD_H_
#include <drivers/defs/usb_armory.h>
#include <drivers/uart/imx.h>
namespace Hw::Usb_armory_board {
using namespace Usb_armory;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* ignored value */
};
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__USB_ARMORY_BOARD_H_ */

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repos/base-hw/src/include/hw/spec/arm/wand_quad_board.h Normal file
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@ -0,0 +1,36 @@
/*
* \brief Wandboard Quad specific definitions
* \author Stefan Kalkowski
* \date 2019-05-16
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__WAND_QUAD_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__WAND_QUAD_BOARD_H_
#include <drivers/defs/wand_quad.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Hw::Wand_quad_board {
using namespace Wand_quad;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_SIZE = UART_1_MMIO_SIZE,
UART_CLOCK = 0, /* dummy value, not used */
};
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__WAND_QUAD_BOARD_H_ */

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repos/base-hw/src/include/hw/spec/arm/zynq_qemu_board.h Normal file
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@ -0,0 +1,33 @@
/*
* \brief Zynq specific board definitions
* \author Stefan Kalkowski
* \date 2019-05-16
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__ZYNQ_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__ZYNQ_BOARD_H_
#include <drivers/defs/zynq_qemu.h>
#include <drivers/uart/xilinx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Hw::Zynq_qemu_board {
using namespace Zynq_qemu;
using L2_cache = Hw::Pl310;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Xilinx_uart;
enum {
UART_BASE = UART_0_MMIO_BASE,
};
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__ZYNQ_BOARD_H_ */

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repos/base-hw/src/include/hw/spec/riscv/board.h Normal file
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@ -0,0 +1,35 @@
/*
* \brief Riscv spike specific board definitions
* \author Stefan Kalkowski
* \date 2019-05-16
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__RISCV__BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__RISCV__BOARD_H_
#include <hw/spec/riscv/page_table.h>
#include <hw/spec/riscv/uart.h>
#include <drivers/defs/riscv.h>
namespace Bootstrap {
struct Cpu {};
struct Pic {};
}
namespace Hw::Riscv_board {
using namespace Riscv;
enum { UART_BASE, UART_CLOCK };
struct Serial : Hw::Riscv_uart {
Serial(Genode::addr_t, Genode::size_t, unsigned) {} };
}
#endif /* _SRC__INCLUDE__HW__SPEC__RISCV__BOARD_H_ */

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repos/base-hw/src/include/hw/spec/x86_64/pc_board.h Normal file
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@ -0,0 +1,30 @@
/*
* \brief PC specific board definitions
* \author Stefan Kalkowski
* \date 2019-05-16
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__X86_64__PC_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__X86_64__PC_BOARD_H_
#include <drivers/uart/x86_pc.h>
namespace Hw::Pc_board {
struct Serial;
enum Dummies { UART_BASE, UART_CLOCK };
}
struct Hw::Pc_board::Serial : Genode::X86_uart
{
Serial(Genode::addr_t, Genode::size_t, unsigned);
};
#endif /* _SRC__BOOTSTRAP__SPEC__X86_64__BOARD_H_ */