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genode/repos/base-hw/src/core/spec/cortex_a9/kernel/cpu.cc

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hw: enable SMP for ARM Cortex A9 This commit enables multi-processing for all Cortex A9 SoCs we currently support. Moreover, it thereby enables the L2 cache for i.MX6 that was not enabled until now. However, the QEMU variants hw_pbxa9 and hw_zynq still only use 1 core, because the busy cpu synchronization used when initializing multiple Cortex A9 cores leads to horrible boot times on QEMU. During this work the CPU initialization in general was reworked. From now on lots of hardware specifics were put into the 'spec' specific files, some generic hook functions and abstractions thereby were eliminated. This results to more lean implementations for instance on non-SMP platforms, or in the x86 case where cache maintainance is a non-issue. Due to the fact that memory/cache coherency and SMP are closely coupled on ARM Cortex A9 this commit combines so different aspects. Fix #1312 Fix #1807
2016-01-11 11:02:52 +01:00
/*
* \brief Cpu class implementation specific to Cortex A9 SMP
* \author Stefan Kalkowski
* \date 2015-12-09
*/
/*
* Copyright (C) 2015-2016 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
/* core includes */
hw: bootstrap into kernel Put the initialization of the cpu cores, setup of page-tables, enabling of MMU and caches into a separate component that is only used to bootstrap the kernel resp. core. Ref #2092
2016-11-07 18:00:24 +01:00
#include <kernel/perf_counter.h>
hw: enable SMP for ARM Cortex A9 This commit enables multi-processing for all Cortex A9 SoCs we currently support. Moreover, it thereby enables the L2 cache for i.MX6 that was not enabled until now. However, the QEMU variants hw_pbxa9 and hw_zynq still only use 1 core, because the busy cpu synchronization used when initializing multiple Cortex A9 cores leads to horrible boot times on QEMU. During this work the CPU initialization in general was reworked. From now on lots of hardware specifics were put into the 'spec' specific files, some generic hook functions and abstractions thereby were eliminated. This results to more lean implementations for instance on non-SMP platforms, or in the x86 case where cache maintainance is a non-issue. Due to the fact that memory/cache coherency and SMP are closely coupled on ARM Cortex A9 this commit combines so different aspects. Fix #1312 Fix #1807
2016-01-11 11:02:52 +01:00
#include <kernel/lock.h>
#include <kernel/pd.h>
#include <pic.h>
hw: bootstrap into kernel Put the initialization of the cpu cores, setup of page-tables, enabling of MMU and caches into a separate component that is only used to bootstrap the kernel resp. core. Ref #2092
2016-11-07 18:00:24 +01:00
#include <platform_pd.h>
hw: enable SMP for ARM Cortex A9 This commit enables multi-processing for all Cortex A9 SoCs we currently support. Moreover, it thereby enables the L2 cache for i.MX6 that was not enabled until now. However, the QEMU variants hw_pbxa9 and hw_zynq still only use 1 core, because the busy cpu synchronization used when initializing multiple Cortex A9 cores leads to horrible boot times on QEMU. During this work the CPU initialization in general was reworked. From now on lots of hardware specifics were put into the 'spec' specific files, some generic hook functions and abstractions thereby were eliminated. This results to more lean implementations for instance on non-SMP platforms, or in the x86 case where cache maintainance is a non-issue. Due to the fact that memory/cache coherency and SMP are closely coupled on ARM Cortex A9 this commit combines so different aspects. Fix #1312 Fix #1807
2016-01-11 11:02:52 +01:00
hw: bootstrap into kernel Put the initialization of the cpu cores, setup of page-tables, enabling of MMU and caches into a separate component that is only used to bootstrap the kernel resp. core. Ref #2092
2016-11-07 18:00:24 +01:00
extern int _mt_begin;
extern int _mt_master_context_begin;
hw: enable SMP for ARM Cortex A9 This commit enables multi-processing for all Cortex A9 SoCs we currently support. Moreover, it thereby enables the L2 cache for i.MX6 that was not enabled until now. However, the QEMU variants hw_pbxa9 and hw_zynq still only use 1 core, because the busy cpu synchronization used when initializing multiple Cortex A9 cores leads to horrible boot times on QEMU. During this work the CPU initialization in general was reworked. From now on lots of hardware specifics were put into the 'spec' specific files, some generic hook functions and abstractions thereby were eliminated. This results to more lean implementations for instance on non-SMP platforms, or in the x86 case where cache maintainance is a non-issue. Due to the fact that memory/cache coherency and SMP are closely coupled on ARM Cortex A9 this commit combines so different aspects. Fix #1312 Fix #1807
2016-01-11 11:02:52 +01:00
hw: bootstrap into kernel Put the initialization of the cpu cores, setup of page-tables, enabling of MMU and caches into a separate component that is only used to bootstrap the kernel resp. core. Ref #2092
2016-11-07 18:00:24 +01:00
void Kernel::Cpu::init(Kernel::Pic &pic)
hw: enable SMP for ARM Cortex A9 This commit enables multi-processing for all Cortex A9 SoCs we currently support. Moreover, it thereby enables the L2 cache for i.MX6 that was not enabled until now. However, the QEMU variants hw_pbxa9 and hw_zynq still only use 1 core, because the busy cpu synchronization used when initializing multiple Cortex A9 cores leads to horrible boot times on QEMU. During this work the CPU initialization in general was reworked. From now on lots of hardware specifics were put into the 'spec' specific files, some generic hook functions and abstractions thereby were eliminated. This results to more lean implementations for instance on non-SMP platforms, or in the x86 case where cache maintainance is a non-issue. Due to the fact that memory/cache coherency and SMP are closely coupled on ARM Cortex A9 this commit combines so different aspects. Fix #1312 Fix #1807
2016-01-11 11:02:52 +01:00
{
pic.init_cpu_local();
hw: bootstrap into kernel Put the initialization of the cpu cores, setup of page-tables, enabling of MMU and caches into a separate component that is only used to bootstrap the kernel resp. core. Ref #2092
2016-11-07 18:00:24 +01:00
static Hw::Address_space invalid_space(nullptr);
Cpu_context * c = (Cpu_context*) (Cpu::exception_entry + ((addr_t)&_mt_master_context_begin - (addr_t)&_mt_begin));
c->cpu_exception = Genode::Cpu::Ttbr0::init((addr_t)invalid_space.translation_table_phys());
hw: re-implement lazy FPU context switch The new implementation of the FPU and FPU context is taken out to separate architecture-dependent header files. The generic Cpu_lazy_state is deleted. There is no hint about the existence of something like an FPU in the generic non-architexture-dependent code anymore. Instead the architecture-dependent CPU context of a thread is extended by an FPU context where supported. Moreover, the current FPU implementations are enhanced so that threads that get deleted now release the FPU when still obtaining it. Fix #1855
2016-01-19 13:33:04 +01:00
_fpu.init();
hw: enable SMP for ARM Cortex A9 This commit enables multi-processing for all Cortex A9 SoCs we currently support. Moreover, it thereby enables the L2 cache for i.MX6 that was not enabled until now. However, the QEMU variants hw_pbxa9 and hw_zynq still only use 1 core, because the busy cpu synchronization used when initializing multiple Cortex A9 cores leads to horrible boot times on QEMU. During this work the CPU initialization in general was reworked. From now on lots of hardware specifics were put into the 'spec' specific files, some generic hook functions and abstractions thereby were eliminated. This results to more lean implementations for instance on non-SMP platforms, or in the x86 case where cache maintainance is a non-issue. Due to the fact that memory/cache coherency and SMP are closely coupled on ARM Cortex A9 this commit combines so different aspects. Fix #1312 Fix #1807
2016-01-11 11:02:52 +01:00
{
Lock::Guard guard(data_lock());
/* enable performance counter */
perf_counter()->enable();
/* enable timer interrupt */
pic.unmask(Timer::interrupt_id(id()), id());
}
}
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