2019-02-18 15:02:54 +01:00
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/*
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* \brief Specific bootstrap implementations
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* \author Stefan Kalkowski
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* \author Josef Soentgen
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* \author Martin Stein
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* \date 2014-02-25
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*/
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/*
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* Copyright (C) 2014-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <platform.h>
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#include <spec/arm/imx_aipstz.h>
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using namespace Board;
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Bootstrap::Platform::Board::Board()
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: early_ram_regions(Memory_region { RAM_BASE, RAM_SIZE }),
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core_mmio(Memory_region { UART_BASE,
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UART_SIZE },
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Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
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CORTEX_A9_PRIVATE_MEM_SIZE },
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Memory_region { PL310_MMIO_BASE,
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PL310_MMIO_SIZE })
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{
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Aipstz aipstz_1(AIPS_1_MMIO_BASE);
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Aipstz aipstz_2(AIPS_2_MMIO_BASE);
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unsigned num_values = sizeof(initial_values) / (2*sizeof(unsigned long));
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for (unsigned i = 0; i < num_values; i++)
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*((volatile unsigned long*)initial_values[i][0]) = initial_values[i][1];
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}
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2019-07-10 15:00:33 +02:00
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bool Board::Cpu::errata(Board::Cpu::Errata err) {
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2019-02-18 15:02:54 +01:00
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return (err == ARM_764369) ? true : false; }
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2019-07-10 15:00:33 +02:00
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void Board::Cpu::wake_up_all_cpus(void * const entry)
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2019-02-18 15:02:54 +01:00
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{
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struct Src : Genode::Mmio
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{
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struct Scr : Register<0x0, 32>
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{
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struct Core_1_reset : Bitfield<14,1> {};
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struct Core_2_reset : Bitfield<15,1> {};
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struct Core_3_reset : Bitfield<16,1> {};
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struct Core_1_enable : Bitfield<22,1> {};
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struct Core_2_enable : Bitfield<23,1> {};
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struct Core_3_enable : Bitfield<24,1> {};
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};
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struct Gpr1 : Register<0x20, 32> {}; /* ep core 0 */
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struct Gpr3 : Register<0x28, 32> {}; /* ep core 1 */
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struct Gpr5 : Register<0x30, 32> {}; /* ep core 2 */
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struct Gpr7 : Register<0x38, 32> {}; /* ep core 3 */
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Src(void * const entry) : Genode::Mmio(SRC_MMIO_BASE)
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{
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write<Gpr3>((Gpr3::access_t)entry);
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write<Gpr5>((Gpr5::access_t)entry);
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write<Gpr7>((Gpr7::access_t)entry);
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Scr::access_t v = read<Scr>();
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Scr::Core_1_enable::set(v,1);
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Scr::Core_1_reset::set(v,1);
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Scr::Core_2_enable::set(v,1);
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Scr::Core_2_reset::set(v,1);
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Scr::Core_3_enable::set(v,1);
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Scr::Core_3_reset::set(v,1);
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write<Scr>(v);
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}
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};
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Src src(entry);
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}
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