2015-03-25 11:12:52 +01:00
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/**
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* \brief AHCI port controller handling
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* \author Sebastian Sumpf
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* \date 2015-04-29
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#include <timer_session/connection.h>
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#include "ata_driver.h"
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#include "atapi_driver.h"
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struct Timer_delayer : Mmio::Delayer, Timer::Connection
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{
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void usleep(unsigned us) { Timer::Connection::usleep(us); }
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};
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Mmio::Delayer &Hba::delayer()
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{
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static Timer_delayer d;
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return d;
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}
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struct Ahci
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{
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/* read device signature */
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enum Signature {
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ATA_SIG = 0x101,
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ATAPI_SIG = 0xeb140101,
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ATAPI_SIG_QEMU = 0xeb140000, /* will be fixed in Qemu */
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};
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Ahci_root &root;
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Platform::Hba &platform_hba = Platform::init(Hba::delayer());
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Hba hba = { platform_hba };
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enum { MAX_PORTS = 32 };
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Port_driver *ports[MAX_PORTS];
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bool port_claimed[MAX_PORTS];
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Signal_rpc_member<Ahci> irq;
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Signal_rpc_member<Ahci> device_ready;
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unsigned ready_count = 0;
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2016-05-24 09:54:03 +02:00
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bool enable_atapi;
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2015-03-25 11:12:52 +01:00
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2016-05-24 09:54:03 +02:00
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Ahci(Ahci_root &root, bool support_atapi)
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2015-03-25 11:12:52 +01:00
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: root(root), irq(root.entrypoint(), *this, &Ahci::handle_irq),
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2016-05-24 09:54:03 +02:00
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device_ready(root.entrypoint(), *this, &Ahci::ready),
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enable_atapi(support_atapi)
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2015-03-25 11:12:52 +01:00
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{
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info();
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/* register irq handler */
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platform_hba.sigh_irq(irq);
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/* initialize HBA (IRQs, memory) */
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hba.init();
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/* search for devices */
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scan_ports();
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}
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2016-05-11 18:21:47 +02:00
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bool atapi(unsigned sig)
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2015-03-25 11:12:52 +01:00
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{
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2016-05-24 09:54:03 +02:00
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return enable_atapi && (sig == ATAPI_SIG_QEMU || sig == ATAPI_SIG);
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2015-03-25 11:12:52 +01:00
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}
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2016-05-11 18:21:47 +02:00
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bool ata(unsigned sig)
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2015-11-12 15:00:39 +01:00
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{
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return sig == ATA_SIG;
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}
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2015-03-25 11:12:52 +01:00
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/**
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* Forward IRQs to ports
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*/
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void handle_irq(unsigned)
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{
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unsigned port_list = hba.read<Hba::Is>();
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while (port_list) {
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unsigned port = log2(port_list);
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port_list &= ~(1U << port);
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ports[port]->handle_irq();
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}
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/* clear status register */
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hba.ack_irq();
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/* ack at interrupt controller */
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platform_hba.ack_irq();
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}
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2016-01-05 15:32:15 +01:00
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void ready(unsigned cnt)
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2015-03-25 11:12:52 +01:00
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{
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2016-01-05 15:32:15 +01:00
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ready_count -= cnt;
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if (ready_count)
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2015-03-25 11:12:52 +01:00
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return;
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/* announce service */
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root.announce();
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}
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void info()
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{
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PINF("\tversion: %x.%04x", hba.read<Hba::Version::Major>(),
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hba.read<Hba::Version::Minor>());
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PINF("\tcommand slots: %u", hba.command_slots());
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2015-10-06 15:36:34 +02:00
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PINF("\tnative command queuing: %s", hba.ncq() ? "yes" : "no");
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2015-03-25 11:12:52 +01:00
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PINF("\t64 bit support: %s", hba.supports_64bit() ? "yes" : "no");
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}
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void scan_ports()
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{
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PINF("\tnumber of ports: %u pi: %x", hba.port_count(), hba.read<Hba::Pi>());
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2015-10-06 15:36:34 +02:00
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unsigned available = hba.read<Hba::Pi>();
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2015-03-25 11:12:52 +01:00
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for (unsigned i = 0; i < hba.port_count(); i++) {
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/* check if port is implemented */
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2015-10-06 15:36:34 +02:00
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if (!(available & (1U << i)))
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2015-03-25 11:12:52 +01:00
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continue;
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Port port(hba, platform_hba, i);
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2015-11-12 15:00:39 +01:00
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/* check for ATA/ATAPI devices */
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2015-03-25 11:12:52 +01:00
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unsigned sig = port.read<Port::Sig>();
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2016-05-11 18:21:47 +02:00
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if (!atapi(sig) && !ata(sig)) {
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2015-11-12 15:00:39 +01:00
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PINF("\t\t#%u: off", i);
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continue;
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}
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port.reset();
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bool enabled = false;
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try { enabled = port.enable(); }
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catch (Port::Not_ready) { PERR("Could not enable port %u", i); }
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2015-03-25 11:12:52 +01:00
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2016-05-11 18:21:47 +02:00
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PINF("\t\t#%u: %s", i, atapi(sig) ? "ATAPI" : "ATA");
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2015-03-25 11:12:52 +01:00
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if (!enabled)
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continue;
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switch (sig) {
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case ATA_SIG:
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ports[i] = new (Genode::env()->heap()) Ata_driver(port, device_ready);
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ready_count++;
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break;
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case ATAPI_SIG:
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case ATAPI_SIG_QEMU:
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ports[i] = new (Genode::env()->heap()) Atapi_driver(port, device_ready);
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ready_count++;
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break;
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default:
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PWRN("Device signature %x unsupported", sig);
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}
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}
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};
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Block::Driver *claim_port(unsigned port_num)
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{
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2016-05-11 18:21:47 +02:00
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if (!avail(port_num))
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2015-03-25 11:12:52 +01:00
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throw -1;
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port_claimed[port_num] = true;
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return ports[port_num];
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}
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void free_port(unsigned port_num)
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{
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port_claimed[port_num] = false;
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}
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2016-05-11 18:21:47 +02:00
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bool avail(unsigned port_num)
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2015-03-25 11:12:52 +01:00
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{
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return port_num < MAX_PORTS && ports[port_num] && !port_claimed[port_num] &&
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ports[port_num]->ready();
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}
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2016-02-11 20:03:38 +01:00
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long device_number(const char *model_num, const char *serial_num)
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{
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for (long port_num = 0; port_num < MAX_PORTS; port_num++) {
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Ata_driver* drv = dynamic_cast<Ata_driver *>(ports[port_num]);
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if (!drv)
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continue;
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if (*drv->model == model_num && *drv->serial == serial_num)
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return port_num;
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}
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return -1;
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}
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2015-03-25 11:12:52 +01:00
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};
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static Ahci *sata_ahci(Ahci *ahci = 0)
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{
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static Ahci *a = ahci;
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return a;
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}
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2016-05-24 09:54:03 +02:00
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void Ahci_driver::init(Ahci_root &root, bool support_atapi)
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2015-03-25 11:12:52 +01:00
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{
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2016-05-24 09:54:03 +02:00
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static Ahci ahci(root, support_atapi);
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2015-03-25 11:12:52 +01:00
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sata_ahci(&ahci);
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}
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Block::Driver *Ahci_driver::claim_port(long device_num)
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{
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return sata_ahci()->claim_port(device_num);
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}
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void Ahci_driver::free_port(long device_num)
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{
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sata_ahci()->free_port(device_num);
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}
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2016-05-11 18:21:47 +02:00
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bool Ahci_driver::avail(long device_num)
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2015-03-25 11:12:52 +01:00
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{
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2016-05-11 18:21:47 +02:00
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return sata_ahci()->avail(device_num);
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2015-03-25 11:12:52 +01:00
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}
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2016-02-11 20:03:38 +01:00
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long Ahci_driver::device_number(char const *model_num, char const *serial_num)
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{
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return sata_ahci()->device_number(model_num, serial_num);
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}
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2015-03-25 11:12:52 +01:00
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