122 lines
2.8 KiB
C
122 lines
2.8 KiB
C
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/*
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* \brief Timer driver for core
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* \author Martin Stein
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* \date 2012-04-23
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*/
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/*
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* Copyright (C) 2012-2017 Kernel Labs GmbH
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*
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* This file is part of the Kernel OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _TIMER_DRIVER_H_
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#define _TIMER_DRIVER_H_
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/* Kernel includes */
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#include <util/mmio.h>
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namespace Kernel { class Timer_driver; }
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/**
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* Timer driver for core
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*/
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struct Kernel::Timer_driver : Genode::Mmio
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{
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enum { TICS_PER_MS = 33333 };
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/**
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* Control register
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*/
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struct Cr : Register<0x0, 32>
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{
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struct En : Bitfield<0, 1> { }; /* enable timer */
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struct En_mod : Bitfield<1, 1> /* reload on enable */
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{
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enum { RELOAD = 1 };
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};
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struct Oci_en : Bitfield<2, 1> { }; /* interrupt on compare */
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struct Rld : Bitfield<3, 1> /* reload or roll-over */
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{
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enum { RELOAD_FROM_LR = 1 };
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};
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struct Prescaler : Bitfield<4, 12> /* clock input divisor */
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{
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enum { DIVIDE_BY_1 = 0 };
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};
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struct Swr : Bitfield<16, 1> { }; /* software reset bit */
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struct Iovw : Bitfield<17, 1> { }; /* enable overwrite */
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struct Dbg_en : Bitfield<18, 1> { }; /* enable in debug mode */
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struct Wait_en : Bitfield<19, 1> { }; /* enable in wait mode */
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struct Doz_en : Bitfield<20, 1> { }; /* enable in doze mode */
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struct Stop_en : Bitfield<21, 1> { }; /* enable in stop mode */
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struct Om : Bitfield<22, 2> /* mode of the output pin */
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{
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enum { DISCONNECTED = 0 };
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};
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struct Clk_src : Bitfield<24, 2> /* select clock input */
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{
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enum { HIGH_FREQ_REF_CLK = 2 };
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};
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/**
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* Register value that configures the timer for a one-shot run
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*/
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static access_t prepare_one_shot()
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{
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return En::bits(0) |
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En_mod::bits(En_mod::RELOAD) |
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Oci_en::bits(1) |
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Rld::bits(Rld::RELOAD_FROM_LR) |
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Prescaler::bits(Prescaler::DIVIDE_BY_1) |
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Swr::bits(0) |
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Iovw::bits(0) |
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Dbg_en::bits(0) |
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Wait_en::bits(0) |
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Doz_en::bits(0) |
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Stop_en::bits(0) |
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Om::bits(Om::DISCONNECTED) |
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Clk_src::bits(Clk_src::HIGH_FREQ_REF_CLK);
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}
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};
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/**
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* Status register
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*/
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struct Sr : Register<0x4, 32>
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{
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struct Ocif : Bitfield<0, 1> { }; /* IRQ status, write 1 clears */
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};
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struct Lr : Register<0x8, 32> { }; /* load value register */
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struct Cmpr : Register<0xc, 32> { }; /* compare value register */
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struct Cnt : Register<0x10, 32> { }; /* counter register */
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/**
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* Disable timer and clear its interrupt output
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*/
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void reset()
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{
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/* wait until ongoing reset operations are finished */
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while (read<Cr::Swr>()) ;
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/* disable timer */
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write<Cr::En>(0);
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/* clear interrupt */
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write<Sr::Ocif>(1);
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}
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Timer_driver(unsigned);
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};
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#endif /* _TIMER_DRIVER_H_ */
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