genode/repos/dde_ipxe/patches/intel.patch

diff --git a/src/drivers/net/intel.c b/src/drivers/net/intel.c
index c3a7d407..5e4eb435 100644
--- a/src/drivers/net/intel.c
+++ b/src/drivers/net/intel.c
@@ -305,6 +305,9 @@ static int intel_reset ( struct intel_nic *intel ) {
 		return 0;
 	}
 
+	/* XXX skip MAC/PHY reset */
+	return 0;
+
 	/* Reset PHY and MAC simultaneously */
 	writel ( ( ctrl | INTEL_CTRL_RST | INTEL_CTRL_PHY_RST ),
 		 intel->regs + INTEL_CTRL );
@@ -953,6 +956,14 @@ static struct pci_device_id intel_nics[] = {
 	PCI_ROM ( 0x8086, 0x1526, "82576-5", "82576", 0 ),
 	PCI_ROM ( 0x8086, 0x1527, "82580-f2", "82580 Fiber", 0 ),
 	PCI_ROM ( 0x8086, 0x1533, "i210", "I210", 0 ),
+	PCI_ROM ( 0x8086, 0x153a, "i217lm", "I217LM", 0 ),
+	PCI_ROM ( 0x8086, 0x1559, "i218v", "I218V", 0 ),
+	PCI_ROM ( 0x8086, 0x155a, "i218lm", "I218LM", 0 ),
+	PCI_ROM ( 0x8086, 0x15a2, "i218lm-3", "I218-LM", 0 ),
+	PCI_ROM ( 0x8086, 0x156f, "i219lm", "I219-LM", 0 ),
+	PCI_ROM ( 0x8086, 0x15b7, "i219lm", "I219-LM", 0 ),
+	PCI_ROM ( 0x8086, 0x15e3, "i219lm", "I219-LM", 0 ),
+	PCI_ROM ( 0x8086, 0x1570, "i219v", "I219V", 0 ),
 	PCI_ROM ( 0x8086, 0x294c, "82566dc-2", "82566DC-2", 0 ),
 	PCI_ROM ( 0x8086, 0x2e6e, "cemedia", "CE Media Processor", 0 ),
 };
diff --git a/src/drivers/net/intel.h b/src/drivers/net/intel.h
index 20b4255e..2a11e1df 100644
--- a/src/drivers/net/intel.h
+++ b/src/drivers/net/intel.h
@@ -138,10 +138,10 @@ enum intel_descriptor_status {
  * Minimum value is 8, since the descriptor ring length must be a
  * multiple of 128.
  */
-#define INTEL_NUM_RX_DESC 8
+#define INTEL_NUM_RX_DESC 256
 
 /** Receive descriptor ring fill level */
-#define INTEL_RX_FILL 4
+#define INTEL_RX_FILL (INTEL_NUM_RX_DESC / 2)
 
 /** Receive buffer length */
 #define INTEL_RX_MAX_LEN 2048
@@ -154,7 +154,7 @@ enum intel_descriptor_status {
  * Descriptor ring length must be a multiple of 16.  ICH8/9/10
  * requires a minimum of 16 TX descriptors.
  */
-#define INTEL_NUM_TX_DESC 16
+#define INTEL_NUM_TX_DESC 256
 
 /** Receive/Transmit Descriptor Base Address Low (offset) */
 #define INTEL_xDBAL 0x00