83 lines
2.0 KiB
C
83 lines
2.0 KiB
C
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/*
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* \brief Kernel support specific for the Versatile VEA9X4
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* \author Stefan Kalkowski
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* \date 2012-10-11
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*/
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/*
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* Copyright (C) 2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _SRC__CORE__VEA9X4__TRUSTZONE__KERNEL_SUPPORT_H_
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#define _SRC__CORE__VEA9X4__TRUSTZONE__KERNEL_SUPPORT_H_
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/* Core includes */
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#include <cortex_a9/cpu/core.h>
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#include <pic/pl390_base.h>
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/**
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* CPU driver
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*/
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class Cpu : public Genode::Cortex_a9 { };
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namespace Kernel
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{
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/* import Genode types */
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typedef Genode::Cortex_a9 Cortex_a9;
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typedef Genode::Pl390_base Pl390_base;
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/**
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* Kernel interrupt-controller
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*/
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class Pic : public Pl390_base
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{
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public:
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/**
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* Constructor
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*/
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Pic() : Pl390_base(Cortex_a9::PL390_DISTRIBUTOR_MMIO_BASE,
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Cortex_a9::PL390_CPU_MMIO_BASE)
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{
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/* configure every shared peripheral interrupt */
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for (unsigned i=MIN_SPI; i <= _max_interrupt; i++) {
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_distr.write<Distr::Icdicr::Edge_triggered>(0, i);
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_distr.write<Distr::Icdipr::Priority>(0, i);
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_distr.write<Distr::Icdiptr::Cpu_targets>(Distr::Icdiptr::Cpu_targets::ALL, i);
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}
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/* disable the priority filter */
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_cpu.write<Cpu::Iccpmr::Priority>(0xff);
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/* signal secure IRQ via FIQ interface */
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_cpu.write<Cpu::Iccicr>(Cpu::Iccicr::Enable_s::bits(1) |
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Cpu::Iccicr::Enable_ns::bits(1) |
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Cpu::Iccicr::Fiq_en::bits(1));
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/* use whole band of prios */
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_cpu.write<Cpu::Iccbpr::Binary_point>(Cpu::Iccbpr::Binary_point::NO_PREEMPTION);
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/* enable device */
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_distr.write<Distr::Icddcr>(Distr::Icddcr::Enable::bits(1));
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}
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/**
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* Mark interrupt i unsecure
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*/
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void unsecure(unsigned i) {
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_distr.write<Distr::Icdisr::Nonsecure>(1, i); }
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};
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/**
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* Kernel timer
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*/
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class Timer : public Cortex_a9::Private_timer { };
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}
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#endif /* _SRC__CORE__VEA9X4__TRUSTZONE__KERNEL_SUPPORT_H_ */
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