72 lines
1.5 KiB
C
72 lines
1.5 KiB
C
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/*
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* \brief Clock control module register description
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* \author Nikolay Golikov <nik@ksyslabs.org>
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* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
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* \date 2013-04-29
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _DRIVERS__PLATFORM__IMX53__CCM_H_
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#define _DRIVERS__PLATFORM__IMX53__CCM_H_
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/* Genode includes */
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#include <util/mmio.h>
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#include <drivers/board_base.h>
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#include <os/attached_io_mem_dataspace.h>
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class Ccm : public Genode::Attached_io_mem_dataspace,
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Genode::Mmio
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{
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private:
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/**
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* Control divider register
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*/
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struct Ccdr : Register<0x4, 32>
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{
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struct Ipu_hs_mask : Bitfield <21, 1> { };
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};
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/**
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* Low power control register
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*/
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struct Clpcr : Register<0x54, 32>
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{
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struct Bypass_ipu_hs : Bitfield<18, 1> { };
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};
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struct Cccr5 : Register<0x7c, 32>
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{
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struct Ipu_clk_en : Bitfield<10, 2> { };
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};
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public:
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Ccm()
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: Genode::Attached_io_mem_dataspace(Genode::Board_base::CCM_BASE,
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Genode::Board_base::CCM_SIZE),
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Genode::Mmio((Genode::addr_t)local_addr<void>()) {}
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void ipu_clk_enable(void)
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{
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write<Cccr5::Ipu_clk_en>(3);
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write<Ccdr::Ipu_hs_mask>(0);
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write<Clpcr::Bypass_ipu_hs>(0);
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}
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void ipu_clk_disable(void)
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{
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write<Cccr5::Ipu_clk_en>(0);
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write<Ccdr::Ipu_hs_mask>(1);
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write<Clpcr::Bypass_ipu_hs>(1);
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}
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};
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#endif /* _DRIVERS__PLATFORM__IMX53__CCM_H_ */
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