4e97a6511b
* Instead of always re-load page-tables when a thread context is switched only do this when another user PD's thread is the next target, core-threads are always executed within the last PD's page-table set * remove the concept of the mode transition * instead map the exception vector once in bootstrap code into kernel's memory segment * when a new page directory is constructed for a user PD, copy over the top-level kernel segment entries on RISCV and X86, on ARM we use a designated page directory register for the kernel segment * transfer the current CPU id from bootstrap to core/kernel in a register to ease first stack address calculation * align cpu context member of threads and vms, because of x86 constraints regarding the stack-pointer loading * introduce Align_at template for members with alignment constraints * let the x86 hardware do part of the context saving in ISS, by passing the thread context into the TSS before leaving to user-land * use one exception vector for all ARM platforms including Arm_v6 Fix #2091 |
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| .. | ||
| base | ||
| cap_session | ||
| cpu | ||
| cpu_session | ||
| cpu_thread | ||
| dataspace | ||
| deprecated | ||
| drivers | ||
| io_mem_session | ||
| io_port_session | ||
| irq_session | ||
| log_session | ||
| parent | ||
| pd_session | ||
| ram_session | ||
| region_map | ||
| rm_session | ||
| rom_session | ||
| root | ||
| session | ||
| spec | ||
| thread | ||
| trace_session | ||
| util | ||
| README | ||
This directory contains include files of interfaces that are exported by components to be used by other components. Each subdirectory corresponds to the component exporting the interface.