Commit Graph

536 Commits

Author SHA1 Message Date
Christian Helmuth
30948a4b0d depot: update recipe hashes 2017-11-06 13:57:25 +01:00
Stefan Kalkowski
be4e34b6b5 hw: unify mmu fault handling
Recent work related to issue 1723 showed that there is potential
to get rid of code duplication in MMU fault handling especially
with regard to ARM cpus.
2017-11-06 13:57:22 +01:00
Stefan Kalkowski
d6a05245f2 hw: remove User_context
Fix #2540
2017-11-06 13:57:20 +01:00
Stefan Kalkowski
0635d5fffb hw: turn Cpu_idle into a Thread
Fix #2539
2017-11-06 13:57:20 +01:00
Stefan Kalkowski
84331ac0f7 hw: remove obsolete Kernel::Cpu_context
Due to the changes when fixing issue #2091 the Kernel::Cpu_context
became superfluent and is not used anymore.

Fix #2538
2017-11-06 13:57:20 +01:00
Alexander Boettcher
4dd5e6b266 hw: enable nx bit handling for arm 2017-11-01 08:39:49 +01:00
Alexander Boettcher
aa1d5a7dd1 hw: enable nx bit handling for x86_64
Issue #1723
2017-11-01 08:39:48 +01:00
Alexander Boettcher
db329b02b5 base: enable executable memory fault handling
Fixes #1723
2017-11-01 08:39:48 +01:00
Christian Helmuth
ee4ee6a8ac depot: update recipe hashes 2017-10-19 13:31:18 +02:00
Stefan Kalkowski
4e97a6511b hw: switch page-tables only when necessary
* Instead of always re-load page-tables when a thread context is switched
  only do this when another user PD's thread is the next target,
  core-threads are always executed within the last PD's page-table set
* remove the concept of the mode transition
* instead map the exception vector once in bootstrap code into kernel's
  memory segment
* when a new page directory is constructed for a user PD, copy over the
  top-level kernel segment entries on RISCV and X86, on ARM we use a designated
  page directory register for the kernel segment
* transfer the current CPU id from bootstrap to core/kernel in a register
  to ease first stack address calculation
* align cpu context member of threads and vms, because of x86 constraints
  regarding the stack-pointer loading
* introduce Align_at template for members with alignment constraints
* let the x86 hardware do part of the context saving in ISS, by passing
  the thread context into the TSS before leaving to user-land
* use one exception vector for all ARM platforms including Arm_v6

Fix #2091
2017-10-19 13:31:18 +02:00
Stefan Kalkowski
ca60e24ad9 hw: run core threads in privileged mode
* introduce new syscall (core-only) to create privileged threads
* take the privilege level of the thread into account
  when doing a context switch
* map kernel segment as accessable for privileged code only

Ref #2091
2017-10-19 13:31:17 +02:00
Stefan Kalkowski
7e47fa58b3 hw: use x86 exception stack unconditionally
Always switch to the "exception stack" instead of having a hardware initiated
stack switch during exceptions/interrupts when the privilege level changes only.
Moreover, this commit increases the exception stack slightly.

Ref #2091
2017-10-19 13:31:17 +02:00
Stefan Kalkowski
42db1e112b hw: introduce kernel/user address space split
* introduces central memory map for core/kernel
* on 32-bit platforms the kernel/core starts at 0x80000000
* on 64-bit platforms the kernel/core starts at 0xffffffc000000000
* mark kernel/core mappings as global ones (tagged TLB)
* move the exception vector to begin of core's binary,
  thereby bootstrap knows from where to map it appropriately
* do not map boot modules into core anymore
* constrain core's virtual heap memory area
* differentiate in between user's and core's main thread's UTCB,
  which now resides inside the kernel segment

Ref #2091
2017-10-19 13:31:17 +02:00
Stefan Kalkowski
362337a9e8 hw: remove bootstrap in clean rules
Ref #2091
2017-10-19 13:31:16 +02:00
Martin Stein
b811ef4331 signal: fix starvation by fast signal contexts
In the past, a signal context, that was chosen for handling by
'Signal_receiver::pending_signal and always triggered again before
the next call of 'pending_signal', caused all other contexts behind
in the list to starve. This was the case because 'pending_signal'
always took the first pending context in its context list.

We avoid this problem now by handling pending signals in a round-robin
fashion instead.

Ref #2532
2017-10-19 13:29:42 +02:00
Christian Helmuth
2ed904faab depot: update recipe hashes 2017-08-30 12:41:43 +02:00
Sebastian Sumpf
f361cb28a5 base-hw: timer support for RISC-V
issue #2423
2017-08-30 10:00:00 +02:00
Sebastian Sumpf
9094517809 base-hw: BBL fix warnings
* fix compile warnings
* added license headers to Genodes' part of BBL

issue #2423
2017-08-30 10:00:00 +02:00
Sebastian Sumpf
e17accb3ba base-hw: RISC-V save/restore 'x29' correctly
* register x29/t4 was not saved and therefore not restored correctly
* change 'warning' to 'error' before '_die' is called

issue #2423
2017-08-30 09:59:59 +02:00
Martin Stein
7f29eff75a hw lapic: find best frequency dynamically
Some x86 machines do have a LAPIC speed < 1000 ticks per millisecond
when configured to use the maximum divider (as it was always the case).
But we need microseconds precision for the timeout framework. Thus,
reduce the divider dynamically until the frequency fullfills our
requirements.

Ref #2400
2017-08-28 16:49:50 +02:00
Martin Stein
d9073a1848 timer/util: generic TIMER_MIN_TICKS_PER_MS
Ref #2400
2017-08-28 16:49:50 +02:00
Martin Stein
399e1586be timer: generic timer_ticks_to_us implementation
There are hardware timers whose frequency can't be expressed as
ticks-per-microsecond integer-value because only a ticks-per-millisecond
integer-value is precise enough. We don't want to use expensive
floating-point values here but nonetheless want to translate from ticks
to time with microseconds precision. Thus, we split the input in two and
translate both parts separately. This way, we can raise precision by
shifting the values to their optimal bit position. Afterwards, the results
are shifted back and merged together again.

As this algorithm is not so trivial anymore and used by at least three
timer drivers (base-hw/x86_64, base-hw/cortex_a9, timer/pit), move it to a
generic header to avoid redundancy.

Ref #2400
2017-08-28 16:49:49 +02:00
Martin Stein
16745946e0 hw pit: fix precision reduction to milliseconds
Due to the simplicity of the algorithm that translated from timer ticks
to time, we lost microseconds precision although the timer allows for it.

Ref #2400
2017-08-28 16:49:49 +02:00
Christian Helmuth
21116803b3 Cleanup warning message from %p 2017-08-28 16:49:48 +02:00
Stefan Kalkowski
08a311b033 hw: make address variables 64-bit safe (fix #2503) 2017-08-28 16:49:46 +02:00
Stefan Kalkowski
ea46c462a4 base: make stack area base specifiable for core
When running core as the kernel inside every component, a separate
stack area for core is needed that is different from the user-land
component's one.

Ref #2091
2017-08-28 16:49:46 +02:00
Stefan Kalkowski
500893e7ec hw: prevent absolute addresses in x86_64 assembler
Ref #2091
2017-08-28 16:49:46 +02:00
Stefan Kalkowski
b8cd58e6a5 hw: enable mappings beyond 4G on x86_64
Fix #2498
2017-08-28 16:49:46 +02:00
Stefan Kalkowski
264e64d3ec hw: prevent segment register re-loading
Fix #2497
2017-08-28 16:49:45 +02:00
Christian Helmuth
7f2087e105 muen: adapt initial IP of genode subject
The entry point changed in "hw: add UEFI boot support" due to the
additional Multiboot2 header.

Issue #2242
2017-08-28 16:49:45 +02:00
Alexander Boettcher
430bde3636 core: remove unmap from rm_client
The flush/unmap of memory is tied to an address space and not to a thread.
Move the handling from the Rm_client to the Adress_space class.

Issue #2209
2017-08-28 16:49:44 +02:00
Alexander Boettcher
6792456e4e hw: provide ACPI infos via platform_info ROM
in uefi/mbi2 boot case

Issue #2242
2017-08-28 16:49:44 +02:00
Alexander Boettcher
972031cbbc hw: add UEFI boot support
via grub2 using multiboot 2

Issue #2242
2017-08-28 16:49:44 +02:00
Martin Stein
23f35370a2 core: generic ROM module initialization
For most base platforms (except linux and sel4), the initialization of
boot modules is the same. Thus, merge this default implementation in the
new unit base/src/core/platform_rom_modules.cc.

Ref #2490
2017-08-28 16:49:36 +02:00
Christian Prochaska
60ae6721db hw_x86_64: read number of I/O redirection table entries from IOAPIC
Fixes #2475
2017-08-23 14:08:37 +02:00
Martin Stein
31af206a8c hw rpi: fix bug that caused bad timer precision
The kernel timer on RPI is able to measure time microseconds-precise.
Howeer, due to a bug, we dropped precision during the ticks-to-time
translation and return only milliseconds-precise time.

Ref #2400
2017-08-23 14:08:37 +02:00
Christian Helmuth
8b073f46df depot: update recipe hashes 2017-08-18 10:25:28 +02:00
Alexander Boettcher
58e4f6cf9d core: add map method to pd_session interface
The method can be used to trigger the eager insertion of page frames into
page tables. Intention: to be used for memory used for DMA.

Issue #2209
2017-08-18 10:24:46 +02:00
Alexander Boettcher
de06eefbac hw: evaluate write fault on RO page
rm_fault.run triggers write on read-only ROM provided by core, which
fails without this patch:

arm - "raised unhandled data abort"
x86 - (silent/invisible) busy loop because write fault gets never resolved
2017-08-17 11:04:22 +02:00
Norman Feske
0d1be4abe2 depot: update recipe hashes 2017-06-29 12:00:04 +02:00
Christian Helmuth
69215bc2fc hw: configure SDHC IRQ secure on imx53_qsb_tz 2017-06-29 11:59:59 +02:00
Adrian-Ken Rueegsegger
c14149b4eb Update Muen port
- Use latest Muen version
- Sync VirtualBox Muen subject state
- Rework Muen download so contrib/muen-* remains untouched after port
  has been prepared
2017-06-29 11:59:58 +02:00
Martin Stein
889db34cc3 hw cortex_a9: fix bug in kernel timer
A bug in the timer-ticks-to-microseconds translation of the kernel timer
caused the user time to periodically get stuck for about 32 milliseconds
and then jump forward to the normal level again.

Ref #2400
2017-06-29 11:59:54 +02:00
Christian Helmuth
6f2afb9b44 hw: prevent warning about conversion narrowing 2017-06-19 12:35:57 +02:00
Stefan Kalkowski
a004462096 hw: fix capability accounting of kernel/core
The recently implemented capability resource trading scheme unfortunately
broke the automated capability memory upgrade mechanism needed by base-hw
kernel/core. This commit splits the capability memory upgrade mechanism
from the PD session ram_quota upgrade, and moves that functionality
into a separate Pd_session::Native_pd interface.

Ref #2398
2017-06-19 12:35:55 +02:00
Martin Stein
685f509a43 timer connection: no interpolation on arm w/o hw
On ARM, we do not have a component-local hardware time-source. The ARM
performance counter has no reliable frequency as the ARM idle command
halts the counter. Thus, we do not do local time interpolation on ARM.
Except we're on the HW kernel. In this case we can read out the kernel
time instead.

Ref #2435
2017-05-31 17:50:28 +02:00
Christian Helmuth
892ede515f depot: update recipe hashes 2017-05-31 16:18:01 +02:00
Sebastian Sumpf
c3cf7f3c3a riscv: ISA-1.9.1 and GCC-6.3.0 adaptions
Adds 1.9.1 support to base-hw

Note:
* the kernel timer is not working
* dynamic linking is currently not supported
2017-05-31 13:16:24 +02:00
Sebastian Sumpf
6c95eb9aff base-hw: RISC-V BBL
The Berkley Boot Loader handles kernel loading and machine mode
2017-05-31 13:16:24 +02:00
Christian Helmuth
8bd0efced6 Remove obsolete RAM/CAP services from run scripts
Adapted launchpad and also the rm_fault and resource_request tests.

Issue #2407
2017-05-31 13:16:22 +02:00